Add regression test for enum items shadowing type identifiers

Check that enum item names can shadow visible type identifiers. Cover plain enum
items as well as the counted and ranged enum item sequence forms.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
This commit is contained in:
Lars-Peter Clausen 2026-07-03 18:13:51 -07:00
parent 0c7341be37
commit 43817251f4
3 changed files with 50 additions and 0 deletions

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@ -0,0 +1,40 @@
// Check that enum item names can shadow visible type identifiers.
typedef int T;
typedef int U;
typedef int V;
module test;
reg failed;
`define check(value, expected, error) \
if ((value) !== (expected)) begin \
$display("FAILED(%0d). %s", `__LINE__, error); \
$display(" expected %0h, got %0h", expected, value); \
failed = 1'b1; \
end
enum {
T = 3,
U[2] = 5,
V[3:4] = 9
} e;
initial begin
failed = 1'b0;
e = T;
`check(e, 3, "Enum item name did not hide typedef");
`check(U0, 5, "Enum item sequence name did not hide typedef");
`check(U1, 6, "Enum item sequence value mismatch");
`check(V3, 9, "Enum item range name did not hide typedef");
`check(V4, 10, "Enum item range value mismatch");
if (!failed) begin
$display("PASSED");
end
end
endmodule

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@ -386,6 +386,7 @@ sv_soft_packed_union_fail1 vvp_tests/sv_soft_packed_union_fail1.json
sv_super_member_fail vvp_tests/sv_super_member_fail.json
sv_type_identifier_ams_name_fields vvp_tests/sv_type_identifier_ams_name_fields.json
sv_type_identifier_config_name vvp_tests/sv_type_identifier_config_name.json
sv_type_identifier_enum_item_name vvp_tests/sv_type_identifier_enum_item_name.json
sv_type_identifier_foreach_name vvp_tests/sv_type_identifier_foreach_name.json
sv_type_identifier_genvar_name vvp_tests/sv_type_identifier_genvar_name.json
sv_type_identifier_modport_name vvp_tests/sv_type_identifier_modport_name.json

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@ -0,0 +1,9 @@
{
"type" : "normal",
"source" : "sv_type_identifier_enum_item_name.v",
"iverilog-args" : [ "-g2005-sv" ],
"vlog95" : {
"__comment" : "Enums are SystemVerilog",
"type" : "CE"
}
}