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https://github.com/steveicarus/iverilog.git
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Support carrying the scope of named begin-end
blocks down to the code generator, and have the vvp code generator use that to support disable.
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+18
-1
@@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT) && !defined(macintosh)
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#ident "$Id: t-dll-api.cc,v 1.80 2002/05/26 01:39:03 steve Exp $"
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#ident "$Id: t-dll-api.cc,v 1.81 2002/05/27 00:08:45 steve Exp $"
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#endif
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# include "config.h"
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@@ -1210,6 +1210,18 @@ extern "C" ivl_statement_type_t ivl_statement_type(ivl_statement_t net)
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return net->type_;
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}
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extern "C" ivl_scope_t ivl_stmt_block_scope(ivl_statement_t net)
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{
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switch (net->type_) {
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case IVL_ST_BLOCK:
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case IVL_ST_FORK:
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return net->u_.block_.scope;
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default:
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assert(0);
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return 0;
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}
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}
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extern "C" unsigned ivl_stmt_block_count(ivl_statement_t net)
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{
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switch (net->type_) {
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@@ -1531,6 +1543,11 @@ extern "C" ivl_statement_t ivl_stmt_sub_stmt(ivl_statement_t net)
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/*
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* $Log: t-dll-api.cc,v $
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* Revision 1.81 2002/05/27 00:08:45 steve
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* Support carrying the scope of named begin-end
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* blocks down to the code generator, and have
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* the vvp code generator use that to support disable.
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*
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* Revision 1.80 2002/05/26 01:39:03 steve
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* Carry Verilog 2001 attributes with processes,
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* all the way through to the ivl_target API.
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