Add XOR operator and catch default case branch

tgt-vhdl/expr.cc

@@ -182,6 +182,8 @@ static vhdl_expr *translate_binary(ivl_expr_t e)
       return translate_shift(lhs, rhs, VHDL_BINOP_SL);
    case 'r':
       return translate_shift(lhs, rhs, VHDL_BINOP_SR);
+   case '^':
+      return translate_numeric(lhs, rhs, VHDL_BINOP_XOR);
    default:
       error("No translation for binary opcode '%c'\n",
             ivl_expr_opcode(e));

tgt-vhdl/stmt.cc

@@ -24,6 +24,7 @@
 #include <cstring>
 #include <cassert>
 #include <sstream>
+#include <typeinfo>
 
 /*
  * VHDL has no real equivalent of Verilog's $finish task. The
@@ -430,10 +431,16 @@ static int draw_case(vhdl_process *proc, stmt_container *container,
    
    int nbranches = ivl_stmt_case_count(stmt);
    for (int i = 0; i < nbranches; i++) {
-      vhdl_expr *when = translate_expr(ivl_stmt_case_expr(stmt, i));
+      vhdl_expr *when;
-      if (NULL == when)
+      ivl_expr_t net = ivl_stmt_case_expr(stmt, i);
-         return 1;
+      if (net) {
-
+         when = translate_expr(net);
+         if (NULL == when)
+            return 1;
+      }
+      else
+         when = new vhdl_var_ref("others", NULL);      
+      
       vhdl_case_branch *branch = new vhdl_case_branch(when);
       vhdlcase->add_branch(branch);
       

tgt-vhdl/vhdl_syntax.cc

@@ -23,6 +23,7 @@
 
 #include <cassert>
 #include <iostream>
+#include <typeinfo>
 
 vhdl_entity::vhdl_entity(const char *name, const char *derived_from,
                          vhdl_arch *arch)
@@ -813,6 +814,9 @@ void vhdl_binop_expr::emit(std::ofstream &of, int level) const
       case VHDL_BINOP_SR:
          of << " srl ";
          break;
+      case VHDL_BINOP_XOR:
+         of << " xor ";
+         break;
       }
 
       (*it)->emit(of, level);

tgt-vhdl/vhdl_syntax.hh

@@ -73,6 +73,7 @@ enum vhdl_binop_t {
    VHDL_BINOP_GT,
    VHDL_BINOP_SL,
    VHDL_BINOP_SR,
+   VHDL_BINOP_XOR,
 };
 
 /*