Fix support for attaching attributes to primitive gates.

Module.cc

@@ -17,10 +17,11 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT)
-#ident "$Id: Module.cc,v 1.7 1999/09/17 02:06:25 steve Exp $"
+#ident "$Id: Module.cc,v 1.8 1999/12/11 05:45:41 steve Exp $"
 #endif
 
 # include  "Module.h"
+# include  "PGate.h"
 # include  "PWire.h"
 
 Module::Module(const string&name, const svector<Module::port_t*>*pp)
@@ -98,9 +99,25 @@ PWire* Module::get_wire(const string&name)
       return 0;
 }
 
+PGate* Module::get_gate(const string&name)
+{
+      for (list<PGate*>::iterator cur = gates_.begin()
+		 ; cur != gates_.end()
+		 ; cur ++ ) {
+
+	    if ((*cur)->get_name() == name)
+		  return *cur;
+      }
+
+      return 0;
+}
+
 
 /*
  * $Log: Module.cc,v $
+ * Revision 1.8  1999/12/11 05:45:41  steve
+ *  Fix support for attaching attributes to primitive gates.
+ *
  * Revision 1.7  1999/09/17 02:06:25  steve
  *  Handle unconnected module ports.
  *

Module.h

@@ -19,7 +19,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT)
-#ident "$Id: Module.h,v 1.10 1999/11/27 19:07:57 steve Exp $"
+#ident "$Id: Module.h,v 1.11 1999/12/11 05:45:41 steve Exp $"
 #endif
 
 # include  <list>
@@ -88,6 +88,7 @@ class Module {
 	// Find a wire by name. This is used for connecting gates to
 	// existing wires, etc.
       PWire* get_wire(const string&name);
+      PGate* get_gate(const string&name);
 
       const list<PWire*>& get_wires() const { return wires_; }
       const list<PGate*>& get_gates() const { return gates_; }
@@ -114,6 +115,9 @@ class Module {
 
 /*
  * $Log: Module.h,v $
+ * Revision 1.11  1999/12/11 05:45:41  steve
+ *  Fix support for attaching attributes to primitive gates.
+ *
  * Revision 1.10  1999/11/27 19:07:57  steve
  *  Support the creation of scopes.
  *

PGate.h

@@ -19,12 +19,14 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT)
-#ident "$Id: PGate.h,v 1.10 1999/09/04 19:11:46 steve Exp $"
+#ident "$Id: PGate.h,v 1.11 1999/12/11 05:45:41 steve Exp $"
 #endif
 
 # include  "svector.h"
 # include  "LineInfo.h"
 # include  "PDelays.h"
+# include  <map>
+# include  <string>
 class PExpr;
 class PUdp;
 class Design;
@@ -62,6 +64,8 @@ class PGate : public LineInfo {
       unsigned pin_count() const { return pins_? pins_->count() : 0; }
       const PExpr*pin(unsigned idx) const { return (*pins_)[idx]; }
 
+      map<string,string> attributes;
+
       virtual void dump(ostream&out) const;
       virtual void elaborate(Design*des, const string&path) const;
 
@@ -180,6 +184,9 @@ class PGModule  : public PGate {
 
 /*
  * $Log: PGate.h,v $
+ * Revision 1.11  1999/12/11 05:45:41  steve
+ *  Fix support for attaching attributes to primitive gates.
+ *
  * Revision 1.10  1999/09/04 19:11:46  steve
  *  Add support for delayed non-blocking assignments.
  *

elaborate.cc

@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT)
-#ident "$Id: elaborate.cc,v 1.133 1999/12/05 02:24:08 steve Exp $"
+#ident "$Id: elaborate.cc,v 1.134 1999/12/11 05:45:41 steve Exp $"
 #endif
 
 /*
@@ -327,7 +327,7 @@ void PGBuiltin::elaborate(Design*des, const string&path) const
 		  break;
 	    }
 
-
+	    cur[idx]->set_attributes(attributes);
 	    cur[idx]->rise_time(rise_time);
 	    cur[idx]->fall_time(fall_time);
 	    cur[idx]->decay_time(decay_time);
@@ -2090,6 +2090,9 @@ Design* elaborate(const map<string,Module*>&modules,
 
 /*
  * $Log: elaborate.cc,v $
+ * Revision 1.134  1999/12/11 05:45:41  steve
+ *  Fix support for attaching attributes to primitive gates.
+ *
  * Revision 1.133  1999/12/05 02:24:08  steve
  *  Synthesize LPM_RAM_DQ for writes into memories.
  *

examples/outff.v

@@ -28,18 +28,19 @@
  * That command causes an outff.xnf and outff.ncf file to be created.
  * Next, make the outff.ngd file with the command:
  *
- *    xnf2ngd -l xilinxun -u outff.xnf outff.ngd
+ *    xnf2ngd -l xilinxun -u outff.xnf outff.ngo
+ *    ngdbuild outff.ngo outff.ngd
  *
  * Finally, map the file to fully render it in the target part. The
  * par command is the step that actually optimizes the design and tries
  * to meet timing constraints.
  *
- *    map -o map.ngd outff.ngd
+ *    map -o map.ncd outff.ngd
  *    par -w map.ncd outff.ncd
  *
  * At this point, you can use the FPGA Editor to edit the outff.ncd
  * file to see that the AND gate is in a CLB and the IOB for pin 150
- * has its flip-flop in use.
+ * has its flip-flop in use, and that gbuf is a global buffer.
  */
 
 module main;
@@ -53,6 +54,13 @@ module main;
       // The par program will map this into a CLB F or G unit.
    and (out, i0, i1);
 
+     // This creates a global clock buffer. Notice how I attach an
+     // attribute to the named gate to force it to be mapped to the
+     // desired XNF device. This device will not be pulled into the
+     // IOB associated with iclk because of the attribute.
+   buf gbuf(clk, iclk);
+   $attribute(gbuf, "XNF-LCA", "GCLK:O,I");
+
       // This is mapped to a DFF. Since o0 is connected to a PAD, it
       // is turned into a OUTFF so that it get placed into an IOB.
    always @(posedge clk) o0 = out;

pform.cc

@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT)
-#ident "$Id: pform.cc,v 1.47 1999/11/23 01:04:57 steve Exp $"
+#ident "$Id: pform.cc,v 1.48 1999/12/11 05:45:41 steve Exp $"
 #endif
 
 # include  "compiler.h"
@@ -555,8 +555,16 @@ void pform_set_function(const string&name, svector<PExpr*>*ra, PFunction *func)
 void pform_set_attrib(const string&name, const string&key, const string&value)
 {
       PWire*cur = pform_cur_module->get_wire(name);
-      assert(cur);
+      if (PWire*cur = pform_cur_module->get_wire(name)) {
-      cur->attributes[key] = value;
+	    cur->attributes[key] = value;
+
+      } else if (PGate*cur = pform_cur_module->get_gate(name)) {
+	    cur->attributes[key] = value;
+
+      } else {
+	    VLerror("Unable to match name for setting attribute.");
+
+      }
 }
 
 /*
@@ -717,6 +725,9 @@ int pform_parse(const char*path, map<string,Module*>&modules,
 
 /*
  * $Log: pform.cc,v $
+ * Revision 1.48  1999/12/11 05:45:41  steve
+ *  Fix support for attaching attributes to primitive gates.
+ *
  * Revision 1.47  1999/11/23 01:04:57  steve
  *  A file name of - means standard input.
  *

xnfio.cc

@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT)
-#ident "$Id: xnfio.cc,v 1.9 1999/11/27 19:07:58 steve Exp $"
+#ident "$Id: xnfio.cc,v 1.10 1999/12/11 05:45:41 steve Exp $"
 #endif
 
 # include  "functor.h"
@@ -209,6 +209,9 @@ static void make_ibuf(Design*des, NetNet*net)
 	    if ((tmp = dynamic_cast<NetLogic*>(idx->get_obj())) == 0)
 		  continue;
 
+	    if (tmp->attribute("XNF-LCA") != "")
+		  continue;
+
 	      // Found a BUF, it is only useable if the only input is
 	      // the signal and there are no other inputs.
 	    if ((tmp->type() == NetLogic::BUF) &&
@@ -282,6 +285,9 @@ void xnfio(Design*des)
 
 /*
  * $Log: xnfio.cc,v $
+ * Revision 1.10  1999/12/11 05:45:41  steve
+ *  Fix support for attaching attributes to primitive gates.
+ *
  * Revision 1.9  1999/11/27 19:07:58  steve
  *  Support the creation of scopes.
  *