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https://github.com/steveicarus/iverilog.git
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Merge branch 'master' into vvp-net-out-rework
Conflicts: vvp/vpi_signal.cc
This commit is contained in:
+8
-7
@@ -238,7 +238,7 @@ vvp_fun_part_var::~vvp_fun_part_var()
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}
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bool vvp_fun_part_var::recv_vec4_(vvp_net_ptr_t port, const vvp_vector4_t&bit,
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long&base, vvp_vector4_t&source,
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int&base, vvp_vector4_t&source,
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vvp_vector4_t&ref)
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{
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long tmp;
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@@ -247,12 +247,13 @@ bool vvp_fun_part_var::recv_vec4_(vvp_net_ptr_t port, const vvp_vector4_t&bit,
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source = bit;
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break;
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case 1:
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// LONG_MIN is before the vector and is used to
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// INT_MIN is before the vector and is used to
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// represent a 'bx value on the select input.
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tmp = LONG_MIN;
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// We need a new &PV<> that knows if the index is signed.
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tmp = INT_MIN;
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// We need a new .part/v that knows if the index is signed.
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// For now this will work for a normal integer value.
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vector4_to_value(bit, tmp, false);
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if (tmp == base) return false;
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if ((int)tmp == base) return false;
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base = tmp;
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break;
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default:
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@@ -264,7 +265,7 @@ bool vvp_fun_part_var::recv_vec4_(vvp_net_ptr_t port, const vvp_vector4_t&bit,
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vvp_vector4_t res (wid_);
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for (unsigned idx = 0 ; idx < wid_ ; idx += 1) {
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long adr = base+idx;
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int adr = base+idx;
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if (adr < 0) continue;
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if ((unsigned)adr >= source.size()) break;
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@@ -313,7 +314,7 @@ void vvp_fun_part_var_sa::recv_vec4_pv(vvp_net_ptr_t port, const vvp_vector4_t&b
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struct vvp_fun_part_var_state_s {
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vvp_fun_part_var_state_s() : base(0) { }
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long base;
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int base;
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vvp_vector4_t source;
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vvp_vector4_t ref;
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};
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