Use gn_system_verilog() where appropriate.

Replace explicit comparisons against generation_flag with calls to
the gn_system_verilog helper function, both for code clarity and
to fix a couple of bugs. Also simplify the implementation of the
function, as we already rely on the generation_flag enumeration
being an ordered list.

compiler.h

@@ -145,7 +145,8 @@ extern int build_library_index(const char*path, bool key_case_sensitive);
 
 /* This is the generation of Verilog that the compiler is asked to
    support. Then there are also more detailed controls for more
-   specific language features. */
+   specific language features. Note that the compiler often assumes
+   this is an ordered list. */
 enum generation_t {
       GN_VER1995  = 1,
       GN_VER2001_NOCONFIG  = 2,
@@ -194,25 +195,19 @@ extern bool gn_strict_expr_width_flag;
    loop. */
 extern bool gn_shared_loop_index_flag;
 
-/* If variables can be converted to uwires by a continuous assignment
+static inline bool gn_system_verilog(void)
-   (assuming no procedural assign, then return true. This will be true
-   for SystemVerilog */
-static inline bool gn_var_can_be_uwire(void)
 {
-      if (generation_flag == GN_VER2005_SV ||
+      if (generation_flag >= GN_VER2005_SV)
-          generation_flag == GN_VER2009  ||
-          generation_flag == GN_VER2012)
 	    return true;
       return false;
 }
 
-static inline bool gn_system_verilog(void)
+/* If variables can be converted to uwires by a continuous assignment
+   (assuming no procedural assign), then return true. This will be true
+   for SystemVerilog */
+static inline bool gn_var_can_be_uwire(void)
 {
-      if (generation_flag == GN_VER2005_SV ||
+      return gn_system_verilog();
-          generation_flag == GN_VER2009  ||
-          generation_flag == GN_VER2012)
-	    return true;
-      return false;
 }
 
 static inline bool gn_modules_nest(void)

lexor.lex

@@ -453,7 +453,7 @@ TU [munpf]
       return BASED_NUMBER;
 }
 \'[01xzXZ] {
-      if (generation_flag < GN_VER2005_SV) {
+      if (!gn_system_verilog()) {
 	    cerr << yylloc.text << ":" << yylloc.first_line << ": warning: "
 		 << "Using SystemVerilog 'N bit vector.  Use at least "
 		 << "-g2005-sv to remove this warning." << endl;
@@ -479,7 +479,7 @@ TU [munpf]
 
   /* This rule handles scaled time values for SystemVerilog. */
 [0-9][0-9_]*(\.[0-9][0-9_]*)?{TU}?s {
-      if(generation_flag & (GN_VER2005_SV | GN_VER2009 | GN_VER2012)) {
+      if (gn_system_verilog()) {
 	    yylval.text = strdupnew(yytext);
 	    return TIME_LITERAL;
       } else REJECT; }
@@ -857,7 +857,7 @@ verinum*make_unsized_binary(const char*txt)
 	    ptr += 1;
       }
 
-      assert((tolower(*ptr) == 'b') || (generation_flag >= GN_VER2005_SV));
+      assert((tolower(*ptr) == 'b') || gn_system_verilog());
       if (tolower(*ptr) == 'b') {
 	    ptr += 1;
       } else {

main.cc

@@ -1125,7 +1125,7 @@ int main(int argc, char*argv[])
 
 	/* Decide if we are going to allow system functions to be called
 	 * as tasks. */
-      if (generation_flag >= GN_VER2005_SV) {
+      if (gn_system_verilog()) {
 	    def_sfunc_as_task = IVL_SFUNC_AS_TASK_WARNING;
       }
 

parse.y

@@ -2241,7 +2241,7 @@ variable_dimension /* IEEE1800-2005: A.2.5 */
       }
   | '[' expression ']'
       { // SystemVerilog canonical range
-	if (generation_flag < GN_VER2005_SV) {
+	if (!gn_system_verilog()) {
 	      warn_count += 1;
 	      cerr << @2 << ": warning: Use of SystemVerilog [size] dimension. "
 		   << "Use at least -g2005-sv to remove this warning." << endl;

pform.cc

@@ -486,7 +486,7 @@ PFunction* pform_push_function_scope(const struct vlltype&loc, const char*name,
       pform_set_scope_timescale(func, loc);
 
       PScopeExtra*scopex = find_nearest_scopex(lexical_scope);
-      if ((scopex == 0) && (generation_flag < GN_VER2005_SV)) {
+      if ((scopex == 0) && !gn_system_verilog()) {
 	    cerr << func->get_fileline() << ": error: function declarations "
 		  "must be contained within a module." << endl;
 	    error_count += 1;
@@ -1257,7 +1257,7 @@ void pform_startmodule(const struct vlltype&loc, const char*name,
 void pform_check_timeunit_prec()
 {
       assert(! pform_cur_module.empty());
-      if ((generation_flag & (GN_VER2005_SV | GN_VER2009 | GN_VER2012)) &&
+      if (gn_system_verilog() &&
           (pform_cur_module.front()->time_unit < pform_cur_module.front()->time_precision)) {
 	    VLerror("error: a timeprecision is missing or is too large!");
       } else assert(pform_cur_module.front()->time_unit >=
@@ -2683,7 +2683,7 @@ void pform_makewire(const struct vlltype&li,
 		    NetNet::Type type,
 		    data_type_t*data_type)
 {
-      if ((lexical_scope == 0) && (generation_flag < GN_VER2005_SV)) {
+      if ((lexical_scope == 0) && !gn_system_verilog()) {
 	    VLerror(li, "error: variable declarations must be contained within a module.");
 	    return;
       }
@@ -2990,7 +2990,7 @@ void pform_set_parameter(const struct vlltype&loc,
 			 LexicalScope::range_t*value_range)
 {
       LexicalScope*scope = lexical_scope;
-      if ((scope == 0) && (generation_flag < GN_VER2005_SV)) {
+      if ((scope == 0) && !gn_system_verilog()) {
 	    VLerror(loc, "error: parameter declarations must be contained within a module.");
 	    return;
       }
@@ -3065,7 +3065,7 @@ void pform_set_localparam(const struct vlltype&loc,
 			  bool signed_flag, list<pform_range_t>*range, PExpr*expr)
 {
       LexicalScope*scope = lexical_scope;
-      if ((scope == 0) && (generation_flag < GN_VER2005_SV)) {
+      if ((scope == 0) && !gn_system_verilog()) {
 	    VLerror(loc, "error: localparam declarations must be contained within a module.");
 	    return;
       }