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Implement real valued signals and arith nodes.

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steve
2005-07-06 04:29:25 +00:00
parent e7f3340513
commit 3ac79c294a
19 changed files with 741 additions and 333 deletions
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vvp/logic.cc
+12 -1
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@@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: logic.cc,v 1.31 2005/06/26 21:08:38 steve Exp $"
#ident "$Id: logic.cc,v 1.32 2005/07/06 04:29:25 steve Exp $"
#endif
# include "logic.h"
@@ -175,6 +175,14 @@ void vvp_fun_bufz::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit)
vvp_send_vec4(ptr.ptr()->out, bit);
}
void vvp_fun_bufz::recv_real(vvp_net_ptr_t ptr, double bit)
{
if (ptr.port() != 0)
return;
vvp_send_real(ptr.ptr()->out, bit);
}
vvp_fun_muxz::vvp_fun_muxz(unsigned wid)
: a_(wid), b_(wid)
{
@@ -377,6 +385,9 @@ void compile_functor(char*label, char*type, unsigned width,
/*
* $Log: logic.cc,v $
* Revision 1.32 2005/07/06 04:29:25 steve
* Implement real valued signals and arith nodes.
*
* Revision 1.31 2005/06/26 21:08:38 steve
* AND functor explicitly knows its width.
*