Handle selects unsized literal values accounting for bit extension.
When selecting bits from unsized literals, we do not put a limit on the size of the literal, so there is no top above which we stop getting literal bits.
This commit is contained in:
Stephen Williams
parent
72b4332b02
commit
3927917133
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@ -2446,6 +2446,186 @@ static void draw_select_signal_dest(ivl_expr_t exp,
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}
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}
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}
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}
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static struct vector_info draw_select_unsized_literal(ivl_expr_t exp,
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unsigned wid,
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int stuff_ok_flag)
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{
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struct vector_info subv, shiv, res;
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ivl_expr_t sube = ivl_expr_oper1(exp);
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ivl_expr_t shift = ivl_expr_oper2(exp);
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assert(!ivl_expr_sized(sube));
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res.wid = wid;
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/* Evaluate the sub-expression. */
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subv = draw_eval_expr(sube, 0);
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/* Special case: Any bit/part select of an unsized constant
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zero by an unsigned base is another constant zero, so short
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circuit and return the value we know. */
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if (subv.base == 0 && !ivl_expr_signed(shift)) {
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fprintf(vvp_out, "; Part select of unsized zero with unsigned shift is zero.\n");
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subv.wid = wid;
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return subv;
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}
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/* Special case: Any bit/part select of an unsized constant -1
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by an unsigned base is another constant -1, so short
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circuit and return the value we know. */
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if (subv.base == 1 && ivl_expr_signed(sube) && !ivl_expr_signed(shift)) {
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fprintf(vvp_out, "; Part select of unsized -1 with unsigned shift is -1.\n");
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subv.wid = wid;
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return subv;
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}
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/* Evaluate the bit select base expression. */
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shiv = draw_eval_expr(shift, STUFF_OK_XZ);
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/* Special case: If the shift is a constant 0, skip the shift
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and return the subexpression with the width trimmed down to
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the part select width. */
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if (shiv.base == 0) {
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fprintf(vvp_out, "; Part select with shift==0 skips shift.\n");
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assert(subv.wid >= wid);
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res.base = subv.base;
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return res;
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}
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/* Special case: If the expression is an unsized zero (and we
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know that the shift is signed) then the expression value is
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0 if the shift is >= 0, and x otherwise. The trickery in
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this special case assumes the output width is 1. */
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if (subv.base==0 && wid==1) {
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assert(ivl_expr_signed(shift));
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if (shiv.base < 4) {
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assert(shiv.base != 0);
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res.base = 2;
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res.wid = wid;
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return res;
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}
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/* Test if the shift is <0 by looking at the sign
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bit. If the sign bit is 1, then it is negative and
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the result is 1'bx. If the sign bit is 0, then the
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result is 1'b0. */
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clr_vector(shiv);
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res.base = allocate_vector(wid);
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res.wid = wid;
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fprintf(vvp_out, " %%mov %u, 2, 1;\n", res.base);
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fprintf(vvp_out, " %%and %u, %u, 1; x if shift<0, 0 otherwise\n",
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res.base, shiv.base+shiv.wid-1);
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return res;
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}
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/* Special case: If the expression is an unsized -1 (and we
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know that the shift is signed) then the expression value is
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1 if the shift is >= 0, and x otherwise. The trickery in
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this special case assumes the output width is 1. */
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if (subv.base==1 && ivl_expr_signed(sube) && wid==1) {
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assert(ivl_expr_signed(shift));
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if (shiv.base < 4) {
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assert(shiv.base != 0);
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res.base = 2;
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res.wid = wid;
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return res;
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}
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/* Test if the shift is <0 by looking at the sign
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bit. If the sign bit is 1, then it is negative and
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the result is 1'bx. If the sign bit is 0, then the
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result is 1'b1. */
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clr_vector(shiv);
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res.base = allocate_vector(wid);
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res.wid = wid;
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fprintf(vvp_out, " %%mov %u, 2, 1;\n", res.base);
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fprintf(vvp_out, " %%nand %u, %u, 1; x if shift<0, 1 otherwise\n",
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res.base, shiv.base+shiv.wid-1);
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return res;
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}
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/* Fall back to doing it the hard way. */
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unsigned lab_end = local_count++;
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unsigned lab_x = local_count++;
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/* Store the bit select base into index register 0, in
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preparation for doing a shift. */
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if (ivl_expr_signed(shift)) {
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fprintf(vvp_out, " %%ix/get/s 0, %u, %u;\n", shiv.base,
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shiv.wid);
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} else {
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fprintf(vvp_out, " %%ix/get 0, %u, %u;\n", shiv.base, shiv.wid);
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}
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clr_vector(shiv);
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/* If we have an undefined index then just produce a 'bx result. */
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fprintf(vvp_out, " %%jmp/1 T_%d.%d, 4;\n", thread_count, lab_x);
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/* If the subv result is a magic constant, then make a copy in
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writable vector space and work from there instead. */
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if (subv.base < 4) {
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res.base = allocate_vector(subv.wid);
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res.wid = subv.wid;
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assert(res.base);
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fprintf(vvp_out, " %%mov %u, %u, %u;\n", res.base,
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subv.base, res.wid);
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subv = res;
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}
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/* If the subv result is narrower then the select width, then
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copy it into a wider vector. */
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if (subv.wid < wid && ivl_expr_signed(sube)) {
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res.base = allocate_vector(wid);
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res.wid = wid;
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assert(res.base);
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fprintf(vvp_out, " %%mov %u, %u, %u; Pad sub-expression to match width\n",
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res.base, subv.base, subv.wid);
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if (ivl_expr_signed(sube)) {
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int idx;
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for (idx = subv.wid ; idx < res.wid ; idx += 1) {
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fprintf(vvp_out, " %%mov %u, %u, 1;\n",
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res.base+idx, subv.base+subv.wid-1);
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}
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} else {
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fprintf(vvp_out, " %%mov %u, 0, %u\n",
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res.base+subv.wid, wid-subv.wid);
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}
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subv = res;
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}
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if (ivl_expr_signed(sube))
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fprintf(vvp_out, " %%shiftr/s/i0 %u, %u; Sign-extending pad\n", subv.base, subv.wid);
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else
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fprintf(vvp_out, " %%shiftr/i0 %u, %u;\n", subv.base, subv.wid);
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fprintf(vvp_out, " %%jmp T_%d.%d;\n", thread_count, lab_end);
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fprintf(vvp_out, "T_%d.%d ; Return 'bx value\n", thread_count, lab_x);
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fprintf(vvp_out, " %%mov %u, 2, %u;\n", subv.base, wid);
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fprintf(vvp_out, " %%jmp T_%d.%d;\n", thread_count, lab_end);
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/* DONE */
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fprintf(vvp_out, "T_%d.%d ;\n", thread_count, lab_end);
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if (subv.wid > wid) {
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res.base = subv.base;
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res.wid = wid;
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subv.base += wid;
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subv.wid -= wid;
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clr_vector(subv);
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} else {
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assert(subv.wid == wid);
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res = subv;
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}
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return res;
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}
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static struct vector_info draw_select_expr(ivl_expr_t exp, unsigned wid,
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static struct vector_info draw_select_expr(ivl_expr_t exp, unsigned wid,
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int stuff_ok_flag)
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int stuff_ok_flag)
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{
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{
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@ -2476,27 +2656,13 @@ static struct vector_info draw_select_expr(ivl_expr_t exp, unsigned wid,
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return res;
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return res;
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}
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}
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/* Evaluate the sub-expression. */
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if (! ivl_expr_sized(sube)) {
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res = draw_select_unsized_literal(exp, wid, stuff_ok_flag);
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return res;
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}
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subv = draw_eval_expr(sube, 0);
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subv = draw_eval_expr(sube, 0);
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/* Special case: Any bit/part select of an unsized constant
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zero by an unsigned base is another constant zero, so short
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circuit and return the value we know. */
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if (subv.base == 0 && !ivl_expr_sized(sube) && !ivl_expr_signed(shift)) {
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fprintf(vvp_out, "; Part select of unsized zero with unsized shift is zero.\n");
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subv.wid = wid;
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return subv;
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}
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/* Special case: Any bit/part select of an unsized constant -1
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by an unsigned base is another constant -1, so short
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circuit and return the value we know. */
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if (subv.base == 1 && ivl_expr_signed(sube) && !ivl_expr_sized(sube) && !ivl_expr_signed(shift)) {
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fprintf(vvp_out, "; Part select of unsized -1 with unsized shift is -1.\n");
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subv.wid = wid;
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return subv;
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}
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/* Evaluate the bit select base expression. */
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/* Evaluate the bit select base expression. */
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shiv = draw_eval_expr(shift, STUFF_OK_XZ);
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shiv = draw_eval_expr(shift, STUFF_OK_XZ);
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@ -2510,60 +2676,6 @@ static struct vector_info draw_select_expr(ivl_expr_t exp, unsigned wid,
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return res;
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return res;
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}
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}
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/* Special case: If the expression is an unsized zero (and we
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know that the shift is signed) then the expression value is
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0 if the shift is >= 0, and x otherwise. The trickery in
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this special case assumes the output width is 1. */
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if (subv.base==0 && !ivl_expr_sized(sube) && wid==1) {
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assert(ivl_expr_signed(shift));
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if (shiv.base < 4) {
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assert(shiv.base != 0);
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res.base = 2;
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res.wid = wid;
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return res;
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}
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/* Test if the shift is <0 by looking at the sign
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bit. If the sign bit is 1, then it is negative and
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the result is 1'bx. If the sign bit is 0, then the
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result is 1'b0. */
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clr_vector(shiv);
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res.base = allocate_vector(wid);
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res.wid = wid;
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fprintf(vvp_out, " %%mov %u, 2, 1;\n", res.base);
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fprintf(vvp_out, " %%and %u, %u, 1; x if shift<0, 0 otherwise\n",
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res.base, shiv.base+shiv.wid-1);
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return res;
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}
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/* Special case: If the expression is an unsized -1 (and we
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know that the shift is signed) then the expression value is
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1 if the shift is >= 0, and x otherwise. The trickery in
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this special case assumes the output width is 1. */
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if (subv.base==1 && ivl_expr_signed(sube) && !ivl_expr_sized(sube) && wid==1) {
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assert(ivl_expr_signed(shift));
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if (shiv.base < 4) {
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assert(shiv.base != 0);
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res.base = 2;
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res.wid = wid;
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return res;
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}
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/* Test if the shift is <0 by looking at the sign
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bit. If the sign bit is 1, then it is negative and
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the result is 1'bx. If the sign bit is 0, then the
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result is 1'b1. */
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clr_vector(shiv);
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res.base = allocate_vector(wid);
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res.wid = wid;
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fprintf(vvp_out, " %%mov %u, 2, 1;\n", res.base);
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fprintf(vvp_out, " %%nand %u, %u, 1; x if shift<0, 1 otherwise\n",
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res.base, shiv.base+shiv.wid-1);
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return res;
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}
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/* Store the bit select base into index register 0, in
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/* Store the bit select base into index register 0, in
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preparation for doing a shift. */
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preparation for doing a shift. */
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if (ivl_expr_signed(shift)) {
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if (ivl_expr_signed(shift)) {
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