Specify correct sensitivity list
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4f472e451e
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@ -150,13 +150,53 @@ static int draw_delay(vhdl_process *proc, ivl_statement_t stmt)
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/*
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/*
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* A wait statement waits for a level change on a @(..) list of
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* A wait statement waits for a level change on a @(..) list of
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* signals. This needs to be implemented by an `if' statement
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* signals.
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* inside the process (which the appropriate signals added to
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* TODO: This won't yet handle the posedge to rising_edge, etc.
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* the sensitivity list).
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* mapping.
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*/
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*/
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static int draw_wait(vhdl_process *proc, ivl_statement_t stmt)
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static int draw_wait(vhdl_process *proc, ivl_statement_t stmt)
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{
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{
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std::cout << "draw_wait" << std::endl;
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int nevents = ivl_stmt_nevent(stmt);
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for (int i = 0; i < nevents; i++) {
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ivl_event_t event = ivl_stmt_events(stmt, i);
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if (ivl_event_nneg(event) != 0)
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error("Negative edge events not supported yet");
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if (ivl_event_npos(event) != 0)
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error("Positive edge events not supported yet");
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int nany = ivl_event_nany(event);
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for (int i = 0; i < nany; i++) {
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ivl_nexus_t nexus = ivl_event_any(event, i);
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std::cout << "event nexus " << ivl_nexus_name(nexus) << std::endl;
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int nptrs = ivl_nexus_ptrs(nexus);
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for (int j = 0; j < nptrs; j++) {
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ivl_nexus_ptr_t nexus_ptr = ivl_nexus_ptr(nexus, j);
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ivl_net_logic_t log;
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ivl_signal_t sig;
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if ((sig = ivl_nexus_ptr_sig(nexus_ptr))) {
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const char *signame = ivl_signal_basename(sig);
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std::cout << "signal " << signame << std::endl;
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proc->add_sensitivity(signame);
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return 0;
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}
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else if ((log = ivl_nexus_ptr_log(nexus_ptr))) {
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error("Nexus points to net logic");
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return 1;
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}
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else {
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error("Nexus points to unknown");
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return 1;
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}
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}
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}
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}
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ivl_statement_t sub_stmt = ivl_stmt_sub_stmt(stmt);
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return 0;
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return 0;
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}
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}
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@ -229,6 +229,11 @@ void vhdl_process::add_decl(vhdl_decl* decl)
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decls_.push_back(decl);
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decls_.push_back(decl);
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}
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}
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void vhdl_process::add_sensitivity(const char *name)
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{
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sens_.push_back(name);
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}
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bool vhdl_process::have_declared_var(const std::string &name) const
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bool vhdl_process::have_declared_var(const std::string &name) const
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{
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{
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decl_list_t::const_iterator it;
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decl_list_t::const_iterator it;
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@ -244,7 +249,21 @@ void vhdl_process::emit(std::ofstream &of, int level) const
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emit_comment(of, level);
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emit_comment(of, level);
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if (name_.size() > 0)
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if (name_.size() > 0)
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of << name_ << ": ";
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of << name_ << ": ";
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of << "process is"; // TODO: sensitivity
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of << "process ";
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int num_sens = sens_.size();
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if (num_sens > 0) {
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of << "(";
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string_list_t::const_iterator it;
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for (it = sens_.begin(); it != sens_.end(); ++it) {
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of << *it;
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if (--num_sens > 0)
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of << ", ";
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}
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of << ") ";
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}
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of << "is";
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emit_children<vhdl_decl>(of, decls_, level);
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emit_children<vhdl_decl>(of, decls_, level);
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of << "begin";
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of << "begin";
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emit_children<vhdl_seq_stmt>(of, stmts_, level);
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emit_children<vhdl_seq_stmt>(of, stmts_, level);
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@ -28,6 +28,8 @@
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class vhdl_entity;
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class vhdl_entity;
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class vhdl_arch;
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class vhdl_arch;
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typedef std::list<std::string> string_list_t;
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/*
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/*
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* Any VHDL syntax element. Each element can also contain a comment.
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* Any VHDL syntax element. Each element can also contain a comment.
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*/
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*/
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@ -246,11 +248,13 @@ public:
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void emit(std::ofstream &of, int level) const;
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void emit(std::ofstream &of, int level) const;
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void add_stmt(vhdl_seq_stmt *stmt);
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void add_stmt(vhdl_seq_stmt *stmt);
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void add_decl(vhdl_decl *decl);
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void add_decl(vhdl_decl *decl);
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void add_sensitivity(const char *name);
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bool have_declared_var(const std::string &name) const;
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bool have_declared_var(const std::string &name) const;
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private:
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private:
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seq_stmt_list_t stmts_;
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seq_stmt_list_t stmts_;
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decl_list_t decls_;
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decl_list_t decls_;
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std::string name_;
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std::string name_;
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string_list_t sens_;
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};
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};
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@ -296,7 +300,7 @@ private:
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std::string name_;
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std::string name_;
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vhdl_arch *arch_; // Entity may only have a single architecture
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vhdl_arch *arch_; // Entity may only have a single architecture
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std::string derived_from_;
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std::string derived_from_;
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std::list<std::string> uses_;
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string_list_t uses_;
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};
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};
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typedef std::list<vhdl_entity*> entity_list_t;
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typedef std::list<vhdl_entity*> entity_list_t;
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