Implement supply->strong strength reduction for non-resistive switches.
As specified in 1364-2005 section 7.11.
This commit is contained in:
Martin Whitaker
parent
69d80839a5
commit
36eef5154f
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2008-2012 Stephen Williams (steve@icarus.com)
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* Copyright (c) 2008-2018 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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@ -45,14 +45,14 @@ struct vvp_island_branch_tran : public vvp_island_branch {
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vvp_island_branch_tran(vvp_net_t*en__, bool active_high__,
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unsigned width__, unsigned part__,
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unsigned offset__);
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unsigned offset__, bool resistive__);
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bool run_test_enabled();
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void run_resolution();
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void run_output();
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vvp_net_t*en;
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unsigned width, part, offset;
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bool active_high;
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bool active_high, resistive;
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tran_state_t state;
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};
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@ -60,9 +60,10 @@ vvp_island_branch_tran::vvp_island_branch_tran(vvp_net_t*en__,
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bool active_high__,
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unsigned width__,
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unsigned part__,
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unsigned offset__)
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unsigned offset__,
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bool resistive__)
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: en(en__), width(width__), part(part__), offset(offset__),
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active_high(active_high__)
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active_high(active_high__), resistive(resistive__)
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{
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state = en__ ? tran_disabled : tran_enabled;
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}
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@ -235,7 +236,8 @@ bool vvp_island_branch_tran::run_test_enabled()
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// input is 'x' or 'z'. We use the rules that are given for MOS switches.
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inline vvp_vector8_t resolve_ambiguous(const vvp_vector8_t&a,
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const vvp_vector8_t&b,
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tran_state_t state)
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tran_state_t state,
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unsigned str_map[8])
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{
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assert(a.size() == b.size());
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vvp_vector8_t out (a.size());
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@ -243,6 +245,9 @@ inline vvp_vector8_t resolve_ambiguous(const vvp_vector8_t&a,
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for (unsigned idx = 0 ; idx < out.size() ; idx += 1) {
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vvp_scalar_t a_bit = a.value(idx);
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vvp_scalar_t b_bit = b.value(idx);
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b_bit = vvp_scalar_t(b_bit.value(),
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str_map[b_bit.strength0()],
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str_map[b_bit.strength1()]);
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if (state == tran_unknown) {
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switch (b_bit.value()) {
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case BIT4_0:
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@ -293,8 +298,8 @@ static void push_value_through_branch(const vvp_vector8_t&val,
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// previously collected (and resolved) for the port.
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if (branch->width == 0) {
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// There are no part selects.
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dst_port->value = resolve_ambiguous(dst_port->value, val,
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branch->state);
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dst_port->value = resolve_ambiguous(dst_port->value, val, branch->state,
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vvp_switch_strength_map[branch->resistive]);
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} else if (dst_ab == 1) {
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// The other side is a strict subset (part select)
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@ -413,7 +418,7 @@ void compile_island_tranif(int sense, char*island, char*pa, char*pb, char*pe)
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vvp_island_branch_tran*br = new vvp_island_branch_tran(en,
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sense ? true :
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false,
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0, 0, 0);
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0, 0, 0, false);
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use_island->add_branch(br, pa, pb);
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@ -430,7 +435,7 @@ void compile_island_tranvp(char*island, char*pa, char*pb,
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free(island);
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vvp_island_branch_tran*br = new vvp_island_branch_tran(NULL, false,
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wid, par, off);
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wid, par, off, false);
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use_island->add_branch(br, pa, pb);
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32
vvp/npmos.cc
32
vvp/npmos.cc
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2005-2016 Stephen Williams (steve@icarus.com)
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* Copyright (c) 2005-2018 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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@ -19,9 +19,10 @@
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# include "npmos.h"
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vvp_fun_pmos_::vvp_fun_pmos_(bool enable_invert)
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vvp_fun_pmos_::vvp_fun_pmos_(bool enable_invert, bool resistive)
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{
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inv_en_ = enable_invert;
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resistive_ = resistive;
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}
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@ -58,12 +59,18 @@ void vvp_fun_pmos_::recv_vec8_pv(vvp_net_ptr_t ptr, const vvp_vector8_t&bit,
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void vvp_fun_pmos_::generate_output_(vvp_net_ptr_t ptr)
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{
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const unsigned*strength_map = vvp_switch_strength_map[resistive_];
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vvp_vector8_t out (bit_.size());
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for (unsigned idx = 0 ; idx < out.size() ; idx += 1) {
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vvp_bit4_t b_en = en_.value(idx);
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vvp_scalar_t b_bit = bit_.value(idx);
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b_bit = vvp_scalar_t(b_bit.value(),
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strength_map[b_bit.strength0()],
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strength_map[b_bit.strength1()]);
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switch (b_en) {
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case BIT4_0:
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out.set_bit(idx, b_bit);
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@ -93,7 +100,7 @@ void vvp_fun_pmos_::generate_output_(vvp_net_ptr_t ptr)
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vvp_fun_pmos::vvp_fun_pmos(bool enable_invert)
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: vvp_fun_pmos_(enable_invert)
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: vvp_fun_pmos_(enable_invert, false)
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{
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}
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@ -112,7 +119,7 @@ void vvp_fun_pmos::recv_vec8(vvp_net_ptr_t ptr, const vvp_vector8_t&bit)
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}
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vvp_fun_rpmos::vvp_fun_rpmos(bool enable_invert)
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: vvp_fun_pmos_(enable_invert)
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: vvp_fun_pmos_(enable_invert, true)
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{
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}
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@ -126,7 +133,7 @@ void vvp_fun_rpmos::recv_vec8(vvp_net_ptr_t ptr, const vvp_vector8_t&bit)
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if (ptr.port() != 0)
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return;
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bit_ = resistive_reduction(bit);
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bit_ = bit;
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generate_output_(ptr);
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}
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@ -135,8 +142,9 @@ void vvp_fun_rpmos::recv_vec8(vvp_net_ptr_t ptr, const vvp_vector8_t&bit)
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* CMOS primitive.
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*/
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vvp_fun_cmos_::vvp_fun_cmos_()
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vvp_fun_cmos_::vvp_fun_cmos_(bool resistive)
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{
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resistive_ = resistive;
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}
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void vvp_fun_cmos_::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t &bit,
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@ -175,6 +183,8 @@ void vvp_fun_cmos_::recv_vec8_pv(vvp_net_ptr_t ptr, const vvp_vector8_t&bit,
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void vvp_fun_cmos_::generate_output_(vvp_net_ptr_t ptr)
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{
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const unsigned*strength_map = vvp_switch_strength_map[resistive_];
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vvp_vector8_t out (bit_.size());
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for (unsigned idx = 0 ; idx < out.size() ; idx += 1) {
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@ -182,6 +192,10 @@ void vvp_fun_cmos_::generate_output_(vvp_net_ptr_t ptr)
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vvp_bit4_t b_p_en = p_en_.value(idx);
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vvp_scalar_t b_bit = bit_.value(idx);
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b_bit = vvp_scalar_t(b_bit.value(),
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strength_map[b_bit.strength0()],
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strength_map[b_bit.strength1()]);
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if (b_n_en == BIT4_1 || b_p_en == BIT4_0) {
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out.set_bit(idx, b_bit);
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} else if (b_n_en == BIT4_0 && b_p_en == BIT4_1) {
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@ -206,7 +220,7 @@ void vvp_fun_cmos_::generate_output_(vvp_net_ptr_t ptr)
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}
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vvp_fun_cmos::vvp_fun_cmos()
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: vvp_fun_cmos_()
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: vvp_fun_cmos_(false)
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{
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}
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@ -225,7 +239,7 @@ void vvp_fun_cmos::recv_vec8(vvp_net_ptr_t ptr, const vvp_vector8_t&bit)
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}
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vvp_fun_rcmos::vvp_fun_rcmos()
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: vvp_fun_cmos_()
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: vvp_fun_cmos_(true)
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{
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}
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@ -239,6 +253,6 @@ void vvp_fun_rcmos::recv_vec8(vvp_net_ptr_t ptr, const vvp_vector8_t&bit)
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if (ptr.port() != 0)
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return;
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bit_ = resistive_reduction(bit);
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bit_ = bit;
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generate_output_(ptr);
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}
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@ -1,7 +1,7 @@
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#ifndef IVL_npmos_H
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#define IVL_npmos_H
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/*
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* Copyright (c) 2005-2016 Stephen Williams (steve@icarus.com)
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* Copyright (c) 2005-2018 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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@ -46,7 +46,7 @@
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class vvp_fun_pmos_ : public vvp_net_fun_t {
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public:
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explicit vvp_fun_pmos_(bool enable_invert);
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explicit vvp_fun_pmos_(bool enable_invert, bool resistive);
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void recv_vec4(vvp_net_ptr_t port, const vvp_vector4_t&bit,
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vvp_context_t);
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@ -62,7 +62,7 @@ class vvp_fun_pmos_ : public vvp_net_fun_t {
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vvp_vector8_t bit_;
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vvp_vector4_t en_;
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bool inv_en_;
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bool inv_en_, resistive_;
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};
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class vvp_fun_pmos : public vvp_fun_pmos_ {
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@ -109,7 +109,7 @@ class vvp_fun_rpmos : public vvp_fun_pmos_ {
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class vvp_fun_cmos_ : public vvp_net_fun_t {
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public:
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explicit vvp_fun_cmos_();
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explicit vvp_fun_cmos_(bool resistive);
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void recv_vec4(vvp_net_ptr_t port, const vvp_vector4_t &bit,
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vvp_context_t);
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@ -126,6 +126,7 @@ class vvp_fun_cmos_ : public vvp_net_fun_t {
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vvp_vector8_t bit_;
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vvp_vector4_t n_en_;
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vvp_vector4_t p_en_;
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bool resistive_;
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};
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class vvp_fun_cmos : public vvp_fun_cmos_ {
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2004-2016 Stephen Williams (steve@icarus.com)
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* Copyright (c) 2004-2018 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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@ -3686,32 +3686,29 @@ vvp_scalar_t fully_featured_resolv_(vvp_scalar_t a, vvp_scalar_t b)
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return res;
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}
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vvp_vector8_t resistive_reduction(const vvp_vector8_t&that)
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{
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static unsigned rstr[8] = {
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0, /* Hi-Z --> Hi-Z */
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1, /* Small capacitance --> Small capacitance */
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1, /* Medium capacitance --> Small capacitance */
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2, /* Weak drive --> Medium capacitance */
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2, /* Large capacitance --> Medium capacitance */
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unsigned vvp_switch_strength_map[2][8] = {
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{ // non-resistive
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0, /* High impedance --> High impedance */
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1, /* Small capacitor --> Small capacitor */
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2, /* Medium capacitor --> Medium capacitor */
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3, /* Weak drive --> Weak drive */
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4, /* Large capacitor --> Large capacitor */
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5, /* Pull drive --> Pull drive */
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6, /* Strong drive --> Strong drive */
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6 /* Supply drive --> Strong drive */
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},
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{ // resistive
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0, /* High impedance --> High impedance */
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1, /* Small capacitor --> Small capacitor */
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1, /* Medium capacitor --> Small capacitor */
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2, /* Weak drive --> Medium capacitor */
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2, /* Large capacitor --> Medium capacitor */
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3, /* Pull drive --> Weak drive */
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5, /* Strong drive --> Pull drive */
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5 /* Supply drive --> Pull drive */
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}
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};
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vvp_vector8_t res (that.size());
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for (unsigned idx = 0 ; idx < res.size() ; idx += 1) {
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vvp_scalar_t bit = that.value(idx);
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bit = vvp_scalar_t(bit.value(),
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rstr[bit.strength0()],
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rstr[bit.strength1()]);
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res.set_bit(idx, bit);
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}
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return res;
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}
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vvp_vector4_t reduce4(const vvp_vector8_t&that)
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{
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vvp_vector4_t out (that.size());
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@ -1,7 +1,7 @@
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#ifndef IVL_vvp_net_H
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#define IVL_vvp_net_H
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/*
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* Copyright (c) 2004-2016 Stephen Williams (steve@icarus.com)
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* Copyright (c) 2004-2018 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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@ -954,9 +954,11 @@ inline vvp_vector8_t resolve(const vvp_vector8_t&a, const vvp_vector8_t&b)
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return out;
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}
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/* This function implements the strength reduction implied by
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Verilog standard resistive devices. */
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extern vvp_vector8_t resistive_reduction(const vvp_vector8_t&a);
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/* This lookup tabke implements the strength reduction implied by
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Verilog standard switch devices. The major dimension selects
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between non-resistive and resistive devices. */
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extern unsigned vvp_switch_strength_map[2][8];
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/* The reduce4 function converts a vector8 to a vector4, losing
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strength information in the process. */
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extern vvp_vector4_t reduce4(const vvp_vector8_t&that);
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