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Smart synthesis of binary AND expressions.

This commit is contained in:
steve 2002-07-07 22:31:39 +00:00
parent 301040a67a
commit 33ee1da817
1 changed files with 24 additions and 1 deletions
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25
expr_synth.cc
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@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) && !defined(macintosh) #if !defined(WINNT) && !defined(macintosh)
#ident "$Id: expr_synth.cc,v 1.34 2002/07/05 21:26:17 steve Exp $" #ident "$Id: expr_synth.cc,v 1.35 2002/07/07 22:31:39 steve Exp $"
#endif #endif
# include "config.h" # include "config.h"
@ -108,6 +108,26 @@ NetNet* NetEBBits::synthesize(Design*des)
string oname = des->local_symbol(path); string oname = des->local_symbol(path);
NetLogic*gate; NetLogic*gate;
/* If the rsig bit is constant, then look for special
cases that I can use to reduce the generated
logic. If I find one, then handle it immediately and
skip the rest of the processing of this bit. */
if (rsig->pin(idx).nexus()->drivers_constant()) {
verinum::V bval = rsig->pin(idx).nexus()->driven_value();
/* (A & 0) is (0) */
if ((op() == '&') && bval == verinum::V0) {
connect(osig->pin(idx), rsig->pin(idx));
continue;
}
/* (A & 1) is A */
if ((op() == '&') && bval == verinum::V1) {
connect(osig->pin(idx), lsig->pin(idx));
continue;
}
}
switch (op()) { switch (op()) {
case '&': case '&':
gate = new NetLogic(scope, oname, 3, NetLogic::AND); gate = new NetLogic(scope, oname, 3, NetLogic::AND);
@ -588,6 +608,9 @@ NetNet* NetESignal::synthesize(Design*des)
/* /*
* $Log: expr_synth.cc,v $ * $Log: expr_synth.cc,v $
* Revision 1.35 2002/07/07 22:31:39 steve
* Smart synthesis of binary AND expressions.
*
* Revision 1.34 2002/07/05 21:26:17 steve * Revision 1.34 2002/07/05 21:26:17 steve
* Avoid emitting to vvp local net symbols. * Avoid emitting to vvp local net symbols.
* *