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Spelling fixes in .txt files

This commit is contained in:
Larry Doolittle 2015-05-20 15:46:04 -07:00 committed by Stephen Williams
parent 358bb4d5d9
commit 33c651aa00
4 changed files with 13 additions and 13 deletions
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2
ivlpp/ivlpp.txt
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@ -95,7 +95,7 @@ keys, with their corresponding values, are:
This is exactly the same as the "-Dname=<value>" described above. This is exactly the same as the "-Dname=<value>" described above.
I:<dir> I:<dir>
This is exctly the same as "-I<dir>". This is exactly the same as "-I<dir>".
relative include:<flag> relative include:<flag>
The <flag> can be "true" or "false". This enables "relative The <flag> can be "true" or "false". This enables "relative

2
tgt-vvp/README.txt
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@ -3,7 +3,7 @@ THE VVP TARGET
SYMBOL NAME CONVENTIONS SYMBOL NAME CONVENTIONS
There are some naming conventions that the vp target uses for There are some naming conventions that the vvp target uses for
generating symbol names. generating symbol names.
* wires and regs * wires and regs

4
vvp/README.txt
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@ -535,8 +535,8 @@ implicit from these numbers. The <symbol> is then the input source.
SUBSTITUTION STATEMENTS: SUBSTITUTION STATEMENTS:
The substition statement doesn't have a direct analog in Verilog, it The substitution statement doesn't have a direct analog in Verilog, it
only turns up in synthesis. It is a sorthand for forms like this: only turns up in synthesis. It is a shorthand for forms like this:
foo = <a>; foo = <a>;
foo[n] = <s>; foo[n] = <s>;

8
vvp/opcodes.txt
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@ -118,7 +118,7 @@ event control registers to determine when to perform the assign.
%evctl is used to set the event control information. %evctl is used to set the event control information.
* %assign/v0 <var-label>, <delay>, <bit> (XXXX Old description) * %assign/v0 <var-label>, <delay>, <bit> (XXXX Old description)
* %assign/v0/d <var-label>, <delayx>, <bit> (XXXX Old description * %assign/v0/d <var-label>, <delayx>, <bit> (XXXX Old description)
* %assign/v0/e <var-label>, <bit> (XXXX Old description) * %assign/v0/e <var-label>, <bit> (XXXX Old description)
The %assign/v0 instruction is a vector version of non-blocking The %assign/v0 instruction is a vector version of non-blocking
@ -142,8 +142,8 @@ assignments. For blocking assignments, see %set/v.
* %assign/vec4/d <var-label>, <delayx> * %assign/vec4/d <var-label>, <delayx>
* %assign/vec4/e <var-label> * %assign/vec4/e <var-label>
The %assign/vec4 instruction if a vec4 version of non-blocking The %assign/vec4 instruction is a vec4 version of non-blocking
assignment, The <delay> is the number lf clock ticks in the future assignment. The <delay> is the number of clock ticks in the future
where the assignment should schedule, and the value to assign is where the assignment should schedule, and the value to assign is
pulled from the vec4 stack. pulled from the vec4 stack.
@ -536,7 +536,7 @@ part comes from the width of the popped value, and the <off> is an
index register that contains the canonical offset where the value index register that contains the canonical offset where the value
sets written. sets written.
The %foce/vec4/off instruction will test the value if flags[4], and if The %force/vec4/off instruction will test the value of flags[4], and if
it is 1, will suppress the actual assignment. This is intended to help it is 1, will suppress the actual assignment. This is intended to help
with detection of invalid index expressions. with detection of invalid index expressions.