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Spellig fixes.

This commit is contained in:
steve 2005-02-19 16:39:30 +00:00
parent 29ebe486b7
commit 327c897d7e
11 changed files with 37 additions and 22 deletions
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2
README.txt
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@ -114,7 +114,7 @@ configure script that modify its behavior:
If you are building for Linux/AMD64 (a.k.a x86_64) then to get the If you are building for Linux/AMD64 (a.k.a x86_64) then to get the
most out of your install, first make sure you have both 64bit and most out of your install, first make sure you have both 64bit and
32bit development libraries installed. Then configure with this 32bit development libraries installed. Then configure with this
somewhat more compilcated command: somewhat more complex command:
./configure libdir64='$(prefix)/lib64' vpidir1=vpi64 vpidir2=. --enable-vvp32 ./configure libdir64='$(prefix)/lib64' vpidir1=vpi64 vpidir2=. --enable-vvp32

7
elab_net.cc
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@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#ifdef HAVE_CVS_IDENT #ifdef HAVE_CVS_IDENT
#ident "$Id: elab_net.cc,v 1.138.2.1 2005/01/29 00:18:23 steve Exp $" #ident "$Id: elab_net.cc,v 1.138.2.2 2005/02/19 16:39:30 steve Exp $"
#endif #endif
# include "config.h" # include "config.h"
@ -1327,7 +1327,7 @@ NetNet* PEConcat::elaborate_net(Design*des, NetScope*scope,
delete etmp; delete etmp;
if (repeat == 0) { if (repeat == 0) {
cerr << get_line() << ": error: Concatenation epeat " cerr << get_line() << ": error: Concatenation repeat "
"may not be 0." "may not be 0."
<< endl; << endl;
des->errors += 1; des->errors += 1;
@ -2517,6 +2517,9 @@ NetNet* PEUnary::elaborate_net(Design*des, NetScope*scope,
/* /*
* $Log: elab_net.cc,v $ * $Log: elab_net.cc,v $
* Revision 1.138.2.2 2005/02/19 16:39:30 steve
* Spellig fixes.
*
* Revision 1.138.2.1 2005/01/29 00:18:23 steve * Revision 1.138.2.1 2005/01/29 00:18:23 steve
* Fix evaluate of constants in netlist concatenation repeats. * Fix evaluate of constants in netlist concatenation repeats.
* *

4
examples/sqrt-virtex.v
View File

@ -16,7 +16,7 @@
* along with this program; if not, write to the Free Software * along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
* *
* $Id: sqrt-virtex.v,v 1.4 2003/11/25 18:35:31 steve Exp $" * $Id: sqrt-virtex.v,v 1.4.2.1 2005/02/19 16:39:32 steve Exp $"
*/ */
/* /*
@ -129,7 +129,7 @@
* This command creates from the chip.ngd the file "chip_root.v" that * This command creates from the chip.ngd the file "chip_root.v" that
* contains Verilog code that simulates the mapped design. This output * contains Verilog code that simulates the mapped design. This output
* Verilog has the single root module "chip_root", which came from the * Verilog has the single root module "chip_root", which came from the
* name of the root module when we were making hte EDIF file in the * name of the root module when we were making the EDIF file in the
* first place. The module has ports named just line the ports of the * first place. The module has ports named just line the ports of the
* chip_root module below. * chip_root module below.
* *

7
expr_synth.cc
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@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#ifdef HAVE_CVS_IDENT #ifdef HAVE_CVS_IDENT
#ident "$Id: expr_synth.cc,v 1.59 2004/06/30 02:16:26 steve Exp $" #ident "$Id: expr_synth.cc,v 1.59.2.1 2005/02/19 16:39:31 steve Exp $"
#endif #endif
# include "config.h" # include "config.h"
@ -408,7 +408,7 @@ NetNet* NetEBDiv::synthesize(Design*des)
default: { default: {
cerr << get_line() << ": internal error: " cerr << get_line() << ": internal error: "
<< "NetEBDiv has unexpeced op() code: " << "NetEBDiv has unexpected op() code: "
<< op() << endl; << op() << endl;
des->errors += 1; des->errors += 1;
@ -875,6 +875,9 @@ NetNet* NetESignal::synthesize(Design*des)
/* /*
* $Log: expr_synth.cc,v $ * $Log: expr_synth.cc,v $
* Revision 1.59.2.1 2005/02/19 16:39:31 steve
* Spellig fixes.
*
* Revision 1.59 2004/06/30 02:16:26 steve * Revision 1.59 2004/06/30 02:16:26 steve
* Implement signed divide and signed right shift in nets. * Implement signed divide and signed right shift in nets.
* *

2
ivlpp/ivlpp.txt
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@ -37,7 +37,7 @@ valid options include:
Predefine the symbol ``name'' to have the specified Predefine the symbol ``name'' to have the specified
value. If the value is not specified, then ``1'' is value. If the value is not specified, then ``1'' is
used. This is mostly of use for controlling conditional used. This is mostly of use for controlling conditional
compilaiton. compilation.
This option does *not* override existing `define This option does *not* override existing `define
directives in the source file. directives in the source file.

7
net_scope.cc
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@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#ifdef HAVE_CVS_IDENT #ifdef HAVE_CVS_IDENT
#ident "$Id: net_scope.cc,v 1.33 2004/10/04 01:10:54 steve Exp $" #ident "$Id: net_scope.cc,v 1.33.2.1 2005/02/19 16:39:31 steve Exp $"
#endif #endif
# include "config.h" # include "config.h"
@ -194,7 +194,7 @@ const NetFuncDef* NetScope::func_def() const
void NetScope::set_module_name(perm_string n) void NetScope::set_module_name(perm_string n)
{ {
assert(type_ == MODULE); assert(type_ == MODULE);
module_name_ = n; /* NOTE: n mus have been permallocated. */ module_name_ = n; /* NOTE: n must have been permallocated. */
} }
perm_string NetScope::module_name() const perm_string NetScope::module_name() const
@ -467,6 +467,9 @@ string NetScope::local_hsymbol()
/* /*
* $Log: net_scope.cc,v $ * $Log: net_scope.cc,v $
* Revision 1.33.2.1 2005/02/19 16:39:31 steve
* Spellig fixes.
*
* Revision 1.33 2004/10/04 01:10:54 steve * Revision 1.33 2004/10/04 01:10:54 steve
* Clean up spurious trailing white space. * Clean up spurious trailing white space.
* *

9
t-dll.cc
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@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#ifdef HAVE_CVS_IDENT #ifdef HAVE_CVS_IDENT
#ident "$Id: t-dll.cc,v 1.131 2004/10/04 01:10:55 steve Exp $" #ident "$Id: t-dll.cc,v 1.131.2.1 2005/02/19 16:39:31 steve Exp $"
#endif #endif
# include "config.h" # include "config.h"
@ -1104,7 +1104,7 @@ void dll_target::lpm_add_sub(const NetAddSub*net)
obj->type = IVL_LPM_SUB; obj->type = IVL_LPM_SUB;
else else
obj->type = IVL_LPM_ADD; obj->type = IVL_LPM_ADD;
obj->name = net->name(); // NetAddSub names are permallocated. obj->name = net->name(); // NetAddSub names are permallocated
assert(net->scope()); assert(net->scope());
obj->scope = find_scope(des_, net->scope()); obj->scope = find_scope(des_, net->scope());
assert(obj->scope); assert(obj->scope);
@ -1803,7 +1803,7 @@ void dll_target::lpm_mux(const NetMux*net)
{ {
ivl_lpm_t obj = new struct ivl_lpm_s; ivl_lpm_t obj = new struct ivl_lpm_s;
obj->type = IVL_LPM_MUX; obj->type = IVL_LPM_MUX;
obj->name = net->name(); // The NetMux perallocates its name. obj->name = net->name(); // NetMux names are permallocated
obj->scope = find_scope(des_, net->scope()); obj->scope = find_scope(des_, net->scope());
assert(obj->scope); assert(obj->scope);
@ -2180,6 +2180,9 @@ extern const struct target tgt_dll = { "dll", &dll_target_obj };
/* /*
* $Log: t-dll.cc,v $ * $Log: t-dll.cc,v $
* Revision 1.131.2.1 2005/02/19 16:39:31 steve
* Spellig fixes.
*
* Revision 1.131 2004/10/04 01:10:55 steve * Revision 1.131 2004/10/04 01:10:55 steve
* Clean up spurious trailing white space. * Clean up spurious trailing white space.
* *

7
tgt-fpga/fpga.txt
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@ -2,7 +2,7 @@
FPGA LOADABLE CODE GENERATOR FOR Icarus Verilog FPGA LOADABLE CODE GENERATOR FOR Icarus Verilog
Copyright 2001 Stephen Williams Copyright 2001 Stephen Williams
$Id: fpga.txt,v 1.11 2003/08/07 05:17:34 steve Exp $ $Id: fpga.txt,v 1.11.2.1 2005/02/19 16:39:32 steve Exp $
The FPGA code generator supports a variety of FPGA devices, writing The FPGA code generator supports a variety of FPGA devices, writing
XNF or EDIF depending on the target. You can select the architecture XNF or EDIF depending on the target. You can select the architecture
@ -44,7 +44,7 @@ map to target gates if desired.
If this is selected, then the output is formatted as an XNF file, If this is selected, then the output is formatted as an XNF file,
suitable for most any type of device. The devices that it emits suitable for most any type of device. The devices that it emits
are generic devices from the unified library. Some devices are macros, are generic devices from the unified library. Some devices are macros,
youmay need to further resolve the generated XNF to get working you may need to further resolve the generated XNF to get working
code for your part. code for your part.
* arch=virtex * arch=virtex
@ -188,6 +188,9 @@ Compile a single-file design with command line tools like so:
--- ---
$Log: fpga.txt,v $ $Log: fpga.txt,v $
Revision 1.11.2.1 2005/02/19 16:39:32 steve
Spellig fixes.
Revision 1.11 2003/08/07 05:17:34 steve Revision 1.11 2003/08/07 05:17:34 steve
Add arch=lpm to the documentation. Add arch=lpm to the documentation.

2
tgt-vvp/README.txt
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@ -3,7 +3,7 @@ THE VVP TARGET
SYMBOL NAME CONVENTIONS SYMBOL NAME CONVENTIONS
There are some naming conventions that the vp target uses for There are some naming conventions that the vvp target uses for
generating symbol names. generating symbol names.
* wires and regs * wires and regs

6
vvp/README.txt
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@ -1,7 +1,7 @@
/* /*
* Copyright (c) 2001 Stephen Williams (steve@icarus.com) * Copyright (c) 2001 Stephen Williams (steve@icarus.com)
* *
* $Id: README.txt,v 1.47 2004/10/04 01:10:58 steve Exp $ * $Id: README.txt,v 1.47.2.1 2005/02/19 16:39:32 steve Exp $
*/ */
VVP SIMULATION ENGINE VVP SIMULATION ENGINE
@ -55,7 +55,7 @@ compiler scales time values ahead of time.
The value is the size of a simulation tick in seconds, and is The value is the size of a simulation tick in seconds, and is
expressed as a power of 10. For example, +0 is 1 second, and -9 is 1 expressed as a power of 10. For example, +0 is 1 second, and -9 is 1
nano-second. If the record is left out, then the precision is taken to nanosecond. If the record is left out, then the precision is taken to
be +0. be +0.
LABELS AND SYMBOLS LABELS AND SYMBOLS
@ -511,7 +511,7 @@ Whereas the arithmetic statements create an array of functor outputs,
there is only one useful functor output for the comparators. That there is only one useful functor output for the comparators. That
functor output is 1 1f the comparison is true, 0 if false, and x functor output is 1 1f the comparison is true, 0 if false, and x
otherwise. The plain versions do unsigned comparison, but the ".s" otherwise. The plain versions do unsigned comparison, but the ".s"
versions to signed comparisons. (Eqlality doesn't need to care about versions do signed comparison. (Equality doesn't need to care about
sign.) sign.)

4
vvp/opcodes.txt
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@ -1,7 +1,7 @@
/* /*
* Copyright (c) 2001-2003 Stephen Williams (steve@icarus.com) * Copyright (c) 2001-2003 Stephen Williams (steve@icarus.com)
* *
* $Id: opcodes.txt,v 1.55 2004/06/19 15:52:53 steve Exp $ * $Id: opcodes.txt,v 1.55.2.1 2005/02/19 16:39:32 steve Exp $
*/ */
@ -193,7 +193,7 @@ Only bit 4 is set by these instructions.
* %cvt/vr <bit-l>, <bit-r>, <wid> * %cvt/vr <bit-l>, <bit-r>, <wid>
Copy a word from r to l, converting it from real to integer (ir) or Copy a word from r to l, converting it from real to integer (ir) or
integer to real (ri) in the process. The source and destinaition may integer to real (ri) in the process. The source and destination may
be the same word address, leading to a convert in place. be the same word address, leading to a convert in place.
The %cvt/vr opcode converts a real word <bit-r> to a thread vector The %cvt/vr opcode converts a real word <bit-r> to a thread vector