Add regression test for variable declarations in unnamed blocks

SystemVerilog supports variable declarations in unnamed blocks, while
Verilog does not.

Add a regression test that checks for this.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>

ivtest/ivltests/unnamed_block_var_decl.v

@@ -0,0 +1,30 @@
+// Check variable declarations in unnamed blocks
+// All of these should pass in SystemVerilog and all but the last should fail in
+// Verilog
+
+module test;
+
+initial begin
+  integer x;
+end
+
+initial begin
+  integer x;
+  integer y;
+end
+
+initial begin
+  integer x, y;
+end
+
+initial begin
+  integer x;
+  integer y;
+  x = y;
+end
+
+initial begin
+  $display("PASSED");
+end
+
+endmodule

ivtest/regress-fsv.list

@@ -82,6 +82,7 @@ pr3015421		CE			ivltests gold=pr3015421-fsv.gold
 resetall		normal,-Wtimescale	ivltests gold=resetall-fsv.gold
 scope2b			normal			ivltests
 sys_func_task_error	RE			ivltests gold=sys_func_task_error-fsv.gold
+unnamed_block_var_decl	normal			ivltests
 
 # We do not run synthesis when forcing SystemVerilog so these pass
 br995			normal			ivltests

ivtest/regress-vlg.list

@@ -1675,6 +1675,7 @@ undef_lval_select4b	CE			ivltests
 undef_lval_select4c	CE			ivltests
 undef_lval_select5	normal			ivltests
 undefined_shift		normal			ivltests
+unnamed_block_var_decl	CE			ivltests
 urand_r			normal			ivltests gold=urand_r.gold
 urand_r2		normal			ivltests gold=urand_r.gold
 urand_r3		normal			ivltests gold=urand_r.gold