Turn the NetESignal into a NetNode so
that it can connect to the netlist. Implement the case statement. Convince t-vvm to output code for the case statement.
This commit is contained in:
steve
parent
8bdd381cdf
commit
30a3953c85
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: design_dump.cc,v 1.11 1999/02/03 04:20:11 steve Exp $"
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#ident "$Id: design_dump.cc,v 1.12 1999/02/08 02:49:56 steve Exp $"
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#endif
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/*
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@ -445,7 +445,14 @@ void NetEIdent::dump(ostream&o) const
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void NetESignal::dump(ostream&o) const
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{
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o << sig_->name();
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o << name();
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}
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void NetESignal::dump_node(ostream&o, unsigned ind) const
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{
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o << setw(ind) << "" << "Expression Node: " << name() << endl;
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dump_node_pins(o, ind+4);
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}
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void NetEUnary::dump(ostream&o) const
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@ -490,6 +497,13 @@ void Design::dump(ostream&o) const
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/*
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* $Log: design_dump.cc,v $
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* Revision 1.12 1999/02/08 02:49:56 steve
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* Turn the NetESignal into a NetNode so
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* that it can connect to the netlist.
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* Implement the case statement.
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* Convince t-vvm to output code for
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* the case statement.
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*
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* Revision 1.11 1999/02/03 04:20:11 steve
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* Parse and elaborate the Verilog CASE statement.
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*
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13
elaborate.cc
13
elaborate.cc
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: elaborate.cc,v 1.13 1999/02/03 04:20:11 steve Exp $"
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#ident "$Id: elaborate.cc,v 1.14 1999/02/08 02:49:56 steve Exp $"
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#endif
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/*
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@ -572,7 +572,9 @@ NetExpr*PEIdent::elaborate_expr(Design*des, const string&path) const
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string name = path+"."+text_;
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NetNet*net = des->find_signal(name);
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assert(net);
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return new NetESignal(net);
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NetESignal*node = new NetESignal(net);
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des->add_node(node);
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return node;
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}
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}
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@ -871,6 +873,13 @@ Design* elaborate(const map<string,Module*>&modules,
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/*
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* $Log: elaborate.cc,v $
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* Revision 1.14 1999/02/08 02:49:56 steve
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* Turn the NetESignal into a NetNode so
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* that it can connect to the netlist.
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* Implement the case statement.
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* Convince t-vvm to output code for
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* the case statement.
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*
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* Revision 1.13 1999/02/03 04:20:11 steve
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* Parse and elaborate the Verilog CASE statement.
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*
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19
emit.cc
19
emit.cc
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: emit.cc,v 1.5 1999/02/01 00:26:49 steve Exp $"
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#ident "$Id: emit.cc,v 1.6 1999/02/08 02:49:56 steve Exp $"
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#endif
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/*
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@ -90,6 +90,11 @@ void NetBlock::emit_proc(ostream&o, struct target_t*tgt) const
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tgt->proc_block(o, this);
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}
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void NetCase::emit_proc(ostream&o, struct target_t*tgt) const
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{
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tgt->proc_case(o, this);
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}
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void NetCondit::emit_proc(ostream&o, struct target_t*tgt) const
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{
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tgt->proc_condit(o, this);
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@ -205,6 +210,11 @@ void NetESignal::expr_scan(struct expr_scan_t*tgt) const
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tgt->expr_signal(this);
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}
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void NetESignal::emit_node(ostream&o, struct target_t*tgt) const
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{
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tgt->net_esignal(o, this);
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}
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void NetEUnary::expr_scan(struct expr_scan_t*tgt) const
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{
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tgt->expr_unary(this);
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@ -224,6 +234,13 @@ void emit(ostream&o, const Design*des, const char*type)
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/*
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* $Log: emit.cc,v $
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* Revision 1.6 1999/02/08 02:49:56 steve
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* Turn the NetESignal into a NetNode so
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* that it can connect to the netlist.
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* Implement the case statement.
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* Convince t-vvm to output code for
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* the case statement.
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*
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* Revision 1.5 1999/02/01 00:26:49 steve
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* Carry some line info to the netlist,
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* Dump line numbers for processes.
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19
netlist.cc
19
netlist.cc
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: netlist.cc,v 1.15 1999/02/03 04:20:11 steve Exp $"
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#ident "$Id: netlist.cc,v 1.16 1999/02/08 02:49:56 steve Exp $"
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#endif
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# include <cassert>
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@ -423,13 +423,21 @@ void NetEConst::set_width(unsigned w)
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expr_width(w);
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}
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NetESignal::NetESignal(NetNet*n)
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: NetExpr(n->pin_count()), NetNode(n->name(), n->pin_count())
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{
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for (unsigned idx = 0 ; idx < n->pin_count() ; idx += 1) {
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connect(pin(idx), n->pin(idx));
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}
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}
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NetESignal::~NetESignal()
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{
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}
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void NetESignal::set_width(unsigned w)
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{
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assert(w == sig_->pin_count());
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assert(w == pin_count());
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expr_width(w);
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}
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@ -873,6 +881,13 @@ NetNet* Design::find_signal(bool (*func)(const NetNet*))
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/*
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* $Log: netlist.cc,v $
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* Revision 1.16 1999/02/08 02:49:56 steve
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* Turn the NetESignal into a NetNode so
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* that it can connect to the netlist.
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* Implement the case statement.
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* Convince t-vvm to output code for
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* the case statement.
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*
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* Revision 1.15 1999/02/03 04:20:11 steve
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* Parse and elaborate the Verilog CASE statement.
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*
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27
netlist.h
27
netlist.h
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@ -19,7 +19,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: netlist.h,v 1.17 1999/02/03 04:20:11 steve Exp $"
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#ident "$Id: netlist.h,v 1.18 1999/02/08 02:49:56 steve Exp $"
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#endif
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/*
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@ -543,7 +543,13 @@ class NetCase : public NetProc {
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void set_case(unsigned idx, NetExpr*ex, NetProc*st);
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//virtual void emit_proc(ostream&, struct target_t*) const;
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const NetExpr*expr() const { return expr_; }
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unsigned nitems() const { return nitems_; }
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const NetExpr*expr(unsigned idx) const { return items_[idx].guard; }
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const NetProc*stat(unsigned idx) const { return items_[idx].statement; }
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virtual void emit_proc(ostream&, struct target_t*) const;
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virtual void dump(ostream&, unsigned ind) const;
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private:
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@ -823,22 +829,22 @@ class NetEIdent : public NetExpr {
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/* When a signal shows up in an expression, this type represents
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it. From this the expression can get any kind of access to the
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structural signal. */
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class NetESignal : public NetExpr {
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class NetESignal : public NetExpr, public NetNode {
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public:
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NetESignal(NetNet*n)
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: NetExpr(n->pin_count()), sig_(n) { }
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NetESignal(NetNet*n);
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~NetESignal();
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const string& name() const { return sig_->name(); }
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const string& name() const { return NetNode::name(); }
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virtual void set_width(unsigned);
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virtual void expr_scan(struct expr_scan_t*) const;
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virtual void emit_node(ostream&, struct target_t*) const;
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virtual void dump(ostream&) const;
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virtual void dump_node(ostream&, unsigned ind) const;
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private:
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NetNet*sig_;
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};
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/*
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@ -953,6 +959,13 @@ extern ostream& operator << (ostream&, NetNet::Type);
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/*
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* $Log: netlist.h,v $
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* Revision 1.18 1999/02/08 02:49:56 steve
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* Turn the NetESignal into a NetNode so
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* that it can connect to the netlist.
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* Implement the case statement.
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* Convince t-vvm to output code for
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* the case statement.
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*
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* Revision 1.17 1999/02/03 04:20:11 steve
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* Parse and elaborate the Verilog CASE statement.
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*
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131
t-vvm.cc
131
t-vvm.cc
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: t-vvm.cc,v 1.9 1999/01/01 01:46:01 steve Exp $"
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#ident "$Id: t-vvm.cc,v 1.10 1999/02/08 02:49:56 steve Exp $"
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#endif
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# include <iostream>
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@ -45,10 +45,12 @@ class target_vvm : public target_t {
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virtual void bufz(ostream&os, const NetBUFZ*);
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virtual void udp(ostream&os, const NetUDP*);
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virtual void net_const(ostream&os, const NetConst*);
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virtual void net_esignal(ostream&os, const NetESignal*);
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virtual void net_pevent(ostream&os, const NetPEvent*);
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virtual void start_process(ostream&os, const NetProcTop*);
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virtual void proc_assign(ostream&os, const NetAssign*);
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virtual void proc_block(ostream&os, const NetBlock*);
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virtual void proc_case(ostream&os, const NetCase*net);
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virtual void proc_condit(ostream&os, const NetCondit*);
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virtual void proc_task(ostream&os, const NetTask*);
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virtual void proc_while(ostream&os, const NetWhile*);
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@ -307,10 +309,10 @@ void target_vvm::signal(ostream&os, const NetNet*sig)
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if (sig->get_ival(idx) == verinum::Vz)
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continue;
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for (NetObj::Link*lnk = sig->pin(0).next_link()
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for (const NetObj::Link*lnk = sig->pin(0).next_link()
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; (*lnk) != sig->pin(0) ; lnk = lnk->next_link()) {
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const NetNode*net;
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if (net = dynamic_cast<const NetNode*>(lnk->get_obj())) {
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if ((net = dynamic_cast<const NetNode*>(lnk->get_obj()))) {
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init_code << " " <<
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mangle(lnk->get_obj()->name()) <<
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".init(" << lnk->get_pin() << ", V" <<
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@ -520,6 +522,10 @@ void target_vvm::net_const(ostream&os, const NetConst*gate)
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emit_gate_outputfun_(gate);
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}
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void target_vvm::net_esignal(ostream&, const NetESignal*)
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{
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}
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/*
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* The net_pevent device is a synthetic device type--a fabrication of
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* the elaboration phase. An event device receives value changes from
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@ -574,18 +580,17 @@ void target_vvm::proc_assign(ostream&os, const NetAssign*net)
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net->find_lval_range(lval, msb, lsb);
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if ((lsb == 0) && (msb == (lval->pin_count()-1))) {
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os << setw(indent_) << "" << "// " << lval->name()
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<< " = ";
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os << " // " << lval->name() << " = ";
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net->rval()->dump(os);
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os << endl;
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os << setw(indent_) << "" << mangle(lval->name())
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os << " " << mangle(lval->name())
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<< " = " << rval << ";" << endl;
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} else {
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assert(0);
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}
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os << setw(indent_) << "" << mangle(lval->name()) <<
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os << " " << mangle(lval->name()) <<
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"_mon.trigger(sim_);" << endl;
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@ -603,15 +608,20 @@ void target_vvm::proc_assign(ostream&os, const NetAssign*net)
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if (dynamic_cast<const NetAssign*>(cur))
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continue;
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// Skip NetESignal nodes. They are handled as
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// expressions.
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if (dynamic_cast<const NetESignal*>(cur))
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continue;
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if (const NetNet*sig = dynamic_cast<const NetNet*>(cur)) {
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os << setw(indent_) << "" << mangle(sig->name())
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os << " " << mangle(sig->name())
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<< "[" << pin << "] = " << rval << "[" << idx
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<< "];" << endl;
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os <<setw(indent_) << "" << mangle(sig->name())
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os << " " << mangle(sig->name())
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<< "_mon.trigger(sim_);" << endl;
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} else {
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os << setw(indent_) << "" << mangle(cur->name()) <<
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os << " " << mangle(cur->name()) <<
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".set(sim_, " << pin << ", " <<
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rval << "[" << idx << "]);" << endl;
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}
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@ -624,19 +634,95 @@ void target_vvm::proc_block(ostream&os, const NetBlock*net)
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net->emit_recurse(os, this);
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}
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/*
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* The code for a case statement introduces basic blocks so causes
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* steps to be created. There is a step for each case, and the
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* out. For example:
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*
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* case (foo)
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* 1 : X;
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* 2 : Y;
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* endcase
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* Z;
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*
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* causes code for Z to be generated, and also code for X and Y that
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* each branch to Z when they finish. X, Y and Z all generate at least
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* one step.
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*/
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void target_vvm::proc_case(ostream&os, const NetCase*net)
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{
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string expr = emit_proc_rval(os, indent_, net->expr());
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ostrstream sc;
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unsigned default_step_ = thread_step_ + 1;
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thread_step_ += 1;
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/* Handle the case statement like a computed goto, where the
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result of the case statements is the next state to go
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to. Once that is done, return true so that statement is
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executed. */
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for (unsigned idx = 0 ; idx < net->nitems() ; idx += 1) {
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string guard = emit_proc_rval(os, indent_, net->expr(idx));
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thread_step_ += 1;
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os << " if (" << expr << ".eequal(" << guard <<
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"))" << endl;
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os << " step_ = &step_" <<
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thread_step_ << "_;" << endl;
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{ unsigned save_indent = indent_;
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indent_ = 8;
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sc << " bool step_" << thread_step_ << "_()" << endl;
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sc << " {" << endl;
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net->stat(idx)->emit_proc(sc, this);
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sc << " step_ = &step_" << default_step_ << "_;" << endl;
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sc << " return true;" << endl;
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sc << " }" << endl;
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indent_ = save_indent;
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}
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}
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os << " else" << endl;
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os << " step_ = &step_" << default_step_ << "_;" << endl;
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os << " return true;" << endl;
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os << " }" << endl;
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os << sc.str();
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os << " bool step_" << default_step_ << "_()" << endl;
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os << " {" << endl;
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}
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void target_vvm::proc_condit(ostream&os, const NetCondit*net)
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{
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unsigned ind = indent_;
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indent_ += 4;
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string expr = emit_proc_rval(os, indent_, net->expr());
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os << setw(ind) << "" << "if (" << expr << "[0] == V1) {" << endl;
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net->emit_recurse_if(os, this);
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os << setw(ind) << "" << "} else {" << endl;
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net->emit_recurse_else(os, this);
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os << setw(ind) << "" << "}" << endl;
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indent_ = ind;
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unsigned if_step = ++thread_step_;
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unsigned else_step = ++thread_step_;
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unsigned out_step = ++thread_step_;
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os << " if (" << expr << "[0] == V1)" << endl;
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os << " step_ = &step_" << if_step << "_;" << endl;
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os << " else" << endl;
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os << " step_ = &step_" << else_step << "_;" << endl;
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os << " return true;" << endl;
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os << " };" << endl;
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os << " bool step_" << if_step << "_()" << endl;
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os << " {" << endl;
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net->emit_recurse_if(os, this);
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os << " step_ = &step_" << out_step << "_;" << endl;
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os << " return true;" << endl;
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os << " }" << endl;
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os << " bool step_" << else_step << "_()" << endl;
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os << " {" << endl;
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net->emit_recurse_else(os, this);
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os << " step_ = &step_" << out_step << "_;" << endl;
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os << " return true;" << endl;
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os << " }" << endl;
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|
||||
os << " bool step_" << out_step << "_()" << endl;
|
||||
os << " {" << endl;
|
||||
}
|
||||
|
||||
void target_vvm::proc_task(ostream&os, const NetTask*net)
|
||||
|
|
@ -778,6 +864,13 @@ extern const struct target tgt_vvm = {
|
|||
};
|
||||
/*
|
||||
* $Log: t-vvm.cc,v $
|
||||
* Revision 1.10 1999/02/08 02:49:56 steve
|
||||
* Turn the NetESignal into a NetNode so
|
||||
* that it can connect to the netlist.
|
||||
* Implement the case statement.
|
||||
* Convince t-vvm to output code for
|
||||
* the case statement.
|
||||
*
|
||||
* Revision 1.9 1999/01/01 01:46:01 steve
|
||||
* Add startup after initialization.
|
||||
*
|
||||
|
|
|
|||
22
target.cc
22
target.cc
|
|
@ -17,7 +17,7 @@
|
|||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
#if !defined(WINNT)
|
||||
#ident "$Id: target.cc,v 1.4 1998/12/01 00:42:15 steve Exp $"
|
||||
#ident "$Id: target.cc,v 1.5 1999/02/08 02:49:56 steve Exp $"
|
||||
#endif
|
||||
|
||||
# include "target.h"
|
||||
|
|
@ -61,6 +61,12 @@ void target_t::net_const(ostream&os, const NetConst*)
|
|||
"Unhandled CONSTANT node." << endl;
|
||||
}
|
||||
|
||||
void target_t::net_esignal(ostream&os, const NetESignal*)
|
||||
{
|
||||
cerr << "target (" << typeid(*this).name() << "): "
|
||||
"Unhandled Expression Signal node." << endl;
|
||||
}
|
||||
|
||||
void target_t::net_pevent(ostream&os, const NetPEvent*)
|
||||
{
|
||||
cerr << "target (" << typeid(*this).name() << "): "
|
||||
|
|
@ -79,6 +85,13 @@ void target_t::proc_block(ostream&os, const NetBlock*)
|
|||
{
|
||||
}
|
||||
|
||||
void target_t::proc_case(ostream&os, const NetCase*cur)
|
||||
{
|
||||
cerr << "target (" << typeid(*this).name() << "): "
|
||||
"Unhandled case:" << endl;
|
||||
cur->dump(cerr, 6);
|
||||
}
|
||||
|
||||
void target_t::proc_condit(ostream&os, const NetCondit*condit)
|
||||
{
|
||||
cerr << "target (" << typeid(*this).name() << "): "
|
||||
|
|
@ -153,6 +166,13 @@ void expr_scan_t::expr_binary(const NetEBinary*ex)
|
|||
|
||||
/*
|
||||
* $Log: target.cc,v $
|
||||
* Revision 1.5 1999/02/08 02:49:56 steve
|
||||
* Turn the NetESignal into a NetNode so
|
||||
* that it can connect to the netlist.
|
||||
* Implement the case statement.
|
||||
* Convince t-vvm to output code for
|
||||
* the case statement.
|
||||
*
|
||||
* Revision 1.4 1998/12/01 00:42:15 steve
|
||||
* Elaborate UDP devices,
|
||||
* Support UDP type attributes, and
|
||||
|
|
|
|||
11
target.h
11
target.h
|
|
@ -19,7 +19,7 @@
|
|||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
#if !defined(WINNT)
|
||||
#ident "$Id: target.h,v 1.4 1998/12/01 00:42:15 steve Exp $"
|
||||
#ident "$Id: target.h,v 1.5 1999/02/08 02:49:56 steve Exp $"
|
||||
#endif
|
||||
|
||||
# include "netlist.h"
|
||||
|
|
@ -64,6 +64,7 @@ struct target_t {
|
|||
virtual void udp(ostream&os, const NetUDP*);
|
||||
virtual void net_assign(ostream&os, const NetAssign*);
|
||||
virtual void net_const(ostream&os, const NetConst*);
|
||||
virtual void net_esignal(ostream&os, const NetESignal*);
|
||||
virtual void net_pevent(ostream&os, const NetPEvent*);
|
||||
|
||||
/* Output a process (called for each process) */
|
||||
|
|
@ -72,6 +73,7 @@ struct target_t {
|
|||
/* Various kinds of process nodes are dispatched through these. */
|
||||
virtual void proc_assign(ostream&os, const NetAssign*);
|
||||
virtual void proc_block(ostream&os, const NetBlock*);
|
||||
virtual void proc_case(ostream&os, const NetCase*);
|
||||
virtual void proc_condit(ostream&os, const NetCondit*);
|
||||
virtual void proc_task(ostream&os, const NetTask*);
|
||||
virtual void proc_while(ostream&os, const NetWhile*);
|
||||
|
|
@ -114,6 +116,13 @@ extern const struct target *target_table[];
|
|||
|
||||
/*
|
||||
* $Log: target.h,v $
|
||||
* Revision 1.5 1999/02/08 02:49:56 steve
|
||||
* Turn the NetESignal into a NetNode so
|
||||
* that it can connect to the netlist.
|
||||
* Implement the case statement.
|
||||
* Convince t-vvm to output code for
|
||||
* the case statement.
|
||||
*
|
||||
* Revision 1.4 1998/12/01 00:42:15 steve
|
||||
* Elaborate UDP devices,
|
||||
* Support UDP type attributes, and
|
||||
|
|
|
|||
Loading…
Reference in New Issue