ivtest: Move some tests to the revress-vvp list

Move some tests from the old structure to the new more descriptive
test suite. Remove them from the old lists.

Documentation/developer/regression_tests.rst

@@ -71,3 +71,9 @@ basename of the gold files, with separate actual gold files for the iverilog
 and vvp stderr and stdout. For example, if a "normal" test includes a gold
 file, then the program is compiled and run, and the outputs are compared with
 the gold file to make sure it ran properly.
+
+iverilog-args (optional)
+^^^^^^^^^^^^^^^^^^^^^^^^
+
+If this is specified, it is a list of strings that are passed as arguments to
+the iverilog command line.

ivtest/ivltests/struct_packed_write_read.v

@@ -62,20 +62,20 @@ module test;
       if (word_sw3      !== 16'b01111111_11111111) begin $display("FAILED -- word_sw3      = 'b%b", word_sw3     ); err=1; end
       // access to parts of structure elements
       if (word_ep0      !== 16'bxxxxxxxx_xxxxxxxx) begin $display("FAILED -- word_ep0      = 'b%b", word_ep0     ); err=1; end
-      if (word_ep1      !== 16'bxxxx1111_xxxx0000) begin $display("FAILED -- word_ep1      = 'b%b", word_ep1     ); err=1; end
+      if (word_ep1      !== 16'bzzzz1111_zzzz0000) begin $display("FAILED -- word_ep1      = 'b%b", word_ep1     ); err=1; end
-      if (word_ep1.high !==  8'bxxxx1111         ) begin $display("FAILED -- word_ep1.high = 'b%b", word_ep1.high); err=1; end
+      if (word_ep1.high !==  8'bzzzz1111         ) begin $display("FAILED -- word_ep1.high = 'b%b", word_ep1.high); err=1; end
-      if (word_ep1.low  !==  8'bxxxx0000         ) begin $display("FAILED -- word_ep1.low  = 'b%b", word_ep1.low ); err=1; end
+      if (word_ep1.low  !==  8'bzzzz0000         ) begin $display("FAILED -- word_ep1.low  = 'b%b", word_ep1.low ); err=1; end
-      if (word_ep2      !== 16'bxxxx1111_xxxx0000) begin $display("FAILED -- word_ep2      = 'b%b", word_ep2     ); err=1; end
+      if (word_ep2      !== 16'bzzzz1111_zzzz0000) begin $display("FAILED -- word_ep2      = 'b%b", word_ep2     ); err=1; end
-      if (word_ep2.high !==  8'bxxxx1111         ) begin $display("FAILED -- word_ep2.high = 'b%b", word_ep2.high); err=1; end
+      if (word_ep2.high !==  8'bzzzz1111         ) begin $display("FAILED -- word_ep2.high = 'b%b", word_ep2.high); err=1; end
-      if (word_ep2.low  !==  8'bxxxx0000         ) begin $display("FAILED -- word_ep2.low  = 'b%b", word_ep2.low ); err=1; end
+      if (word_ep2.low  !==  8'bzzzz0000         ) begin $display("FAILED -- word_ep2.low  = 'b%b", word_ep2.low ); err=1; end
-      if (word_ep3      !== 16'bxxxx0111_xxxx0000) begin $display("FAILED -- word_ep3      = 'b%b", word_ep3     ); err=1; end
+      if (word_ep3      !== 16'bzzzz0111_zzzz0000) begin $display("FAILED -- word_ep3      = 'b%b", word_ep3     ); err=1; end
-      if (word_ep3.high !==  8'bxxxx0111         ) begin $display("FAILED -- word_ep3.high = 'b%b", word_ep3.high); err=1; end
+      if (word_ep3.high !==  8'bzzzz0111         ) begin $display("FAILED -- word_ep3.high = 'b%b", word_ep3.high); err=1; end
-      if (word_ep3.low  !==  8'bxxxx0000         ) begin $display("FAILED -- word_ep3.low  = 'b%b", word_ep3.low ); err=1; end
+      if (word_ep3.low  !==  8'bzzzz0000         ) begin $display("FAILED -- word_ep3.low  = 'b%b", word_ep3.low ); err=1; end
       // access to parts of the whole structure
       if (word_sp0      !== 16'bxxxxxxxx_xxxxxxxx) begin $display("FAILED -- word_sp0      = 'b%b", word_sp0     ); err=1; end
-      if (word_sp1      !== 16'bxxxx1111_1111xxxx) begin $display("FAILED -- word_sp1      = 'b%b", word_sp1     ); err=1; end
+      if (word_sp1      !== 16'bzzzz1111_1111zzzz) begin $display("FAILED -- word_sp1      = 'b%b", word_sp1     ); err=1; end
-      if (word_sp2      !== 16'bxxxx1111_1111xxxx) begin $display("FAILED -- word_sp2      = 'b%b", word_sp2     ); err=1; end
+      if (word_sp2      !== 16'bzzzz1111_1111zzzz) begin $display("FAILED -- word_sp2      = 'b%b", word_sp2     ); err=1; end
-      if (word_sp3      !== 16'bxxxx0111_1111xxxx) begin $display("FAILED -- word_sp3      = 'b%b", word_sp3     ); err=1; end
+      if (word_sp3      !== 16'bzzzz0111_1111zzzz) begin $display("FAILED -- word_sp3      = 'b%b", word_sp3     ); err=1; end
 
       if (!err) $display("PASSED");
    end

ivtest/regress-fsv.list

@@ -99,9 +99,6 @@ br_gh306b			normal			ivltests
 case5-syn-fail			normal			ivltests
 casesynth7			normal			ivltests
 casesynth8			normal			ivltests
-dffsynth			normal			ivltests
-dffsynth8			normal			ivltests
-memsynth1			normal			ivltests
 memsynth2			normal			ivltests
 memsynth3			normal			ivltests
 memsynth5			normal			ivltests

ivtest/regress-sv.list

@@ -516,7 +516,6 @@ struct_packed_queue_fail CE,-g2009		ivltests
 struct_packed_sysfunct	normal,-g2009		ivltests
 struct_packed_sysfunct2	normal,-g2009		ivltests
 struct_packed_uarray_fail CE,-g2009		ivltests
-struct_packed_write_read2	normal,-g2009	ivltests
 struct_invalid_member	CE,-g2009		ivltests gold=struct_invalid_member.gold
 struct_signed		normal,-g2009		ivltests
 sv-constants		normal,-g2005-sv	ivltests

ivtest/regress-synth.list

@@ -94,9 +94,6 @@ br_gh99x		normal			ivltests
 br_gh115		normal			ivltests
 br_gh306a		CE			ivltests
 br_gh306b		CE			ivltests
-case1			normal			ivltests
-case2			normal			ivltests
-case3			normal			ivltests
 case4			normal			ivltests
 case5			normal			ivltests
 case5-syn-fail		CE			ivltests
@@ -112,22 +109,10 @@ casesynth6		normal			ivltests
 casesynth7		normal			ivltests gold=casesynth7.gold
 casesynth8		CE			ivltests
 casesynth9		normal			ivltests
-casex_synth		normal			ivltests
 condit1			normal			ivltests
 conditsynth1		normal			ivltests
 conditsynth2		normal			ivltests
 conditsynth3		normal			ivltests
-dffsynth		normal			ivltests
-dffsynth2		normal			ivltests
-dffsynth3		normal			ivltests
-dffsynth4		normal			ivltests
-dffsynth5		normal			ivltests
-dffsynth6		normal			ivltests
-dffsynth7		normal			ivltests
-dffsynth8		CE			ivltests
-dffsynth9		normal			ivltests
-dffsynth10		normal			ivltests
-dffsynth11		normal			ivltests
 ff_dual_enable		normal			ivltests
 for_loop_synth		normal			ivltests
 for_loop_synth2		normal			ivltests
@@ -138,7 +123,6 @@ inside_synth2		normal			ivltests
 inside_synth3		normal			ivltests
 land5			normal			ivltests
 lcatsynth		normal			ivltests
-memsynth1		normal			ivltests
 memsynth2		normal			ivltests
 memsynth3		normal			ivltests
 memsynth4		normal			ivltests

ivtest/regress-v10.list

@@ -289,8 +289,6 @@ br_gh115		CE,-S			ivltests
 basiclatch		normal			ivltests
 blocksynth2		normal			ivltests
 blocksynth3		normal			ivltests
-case1			normal			ivltests
-case2			normal			ivltests
 case4			normal			ivltests
 case5			normal			ivltests
 case5-syn-fail		normal			ivltests
@@ -299,20 +297,13 @@ casesynth1		normal			ivltests
 casesynth2		normal			ivltests
 casesynth3		normal			ivltests
 casesynth7		NI
-casex_synth		normal			ivltests
 condit1			normal			ivltests
 conditsynth1		normal			ivltests
 conditsynth2		normal			ivltests
 conditsynth3		normal			ivltests
-dffsynth		normal			ivltests
+
-dffsynth3		normal			ivltests
-dffsynth4		normal			ivltests
-dffsynth9		normal			ivltests
-dffsynth10		normal			ivltests
-dffsynth11		normal			ivltests
 inside_synth		normal			ivltests
 inside_synth3		normal			ivltests
-memsynth1		normal			ivltests
 memsynth2		normal			ivltests
 memsynth3		normal			ivltests
 memsynth5		normal			ivltests

ivtest/regress-v11.list

@@ -87,8 +87,6 @@ sv_default_port_value3	CE,-g2009	ivltests
 br_gh440		CE,-g2009	ivltests gold=br_gh440-v11.gold
 
 # v11 has incomplete synthesis support
-dffsynth		CE,-S		ivltests
-memsynth1		CE,-S		ivltests
 memsynth2		CE,-S		ivltests
 memsynth3		CE,-S		ivltests
 memsynth5		CE,-S		ivltests
@@ -97,11 +95,6 @@ memsynth7		CE,-S		ivltests
 memsynth9		CE,-S		ivltests
 mix_reset		CE,-S		ivltests
 
-# These tests pass, but synthesis is creating unnecessary latches.
-case1			normal		ivltests
-case2			normal		ivltests
-casex_synth		normal		ivltests
-
 # For V11 vvp does not fail for these tests
 automatic_error11	normal		ivltests gold=automatic_error11.gold
 automatic_error12	normal		ivltests gold=automatic_error12.gold

ivtest/regress-v12.list

@@ -68,8 +68,6 @@
 #
 
 # v11 has incomplete synthesis support
-dffsynth		CE,-S			ivltests
-memsynth1		CE,-S			ivltests
 memsynth2		CE,-S			ivltests
 memsynth3		CE,-S			ivltests
 memsynth5		CE,-S			ivltests
@@ -77,8 +75,3 @@ memsynth6		CE,-S			ivltests
 memsynth7		CE,-S			ivltests
 memsynth9		CE,-S			ivltests
 mix_reset		CE,-S			ivltests
-
-# These tests pass, but synthesis is creating unnecessary latches.
-case1			normal			ivltests
-case2			normal			ivltests
-casex_synth		normal			ivltests

ivtest/regress-v13.list

@@ -68,8 +68,6 @@
 #
 
 # v13 has incomplete synthesis support
-dffsynth		CE,-S			ivltests
-memsynth1		CE,-S			ivltests
 memsynth2		CE,-S			ivltests
 memsynth3		CE,-S			ivltests
 memsynth5		CE,-S			ivltests
@@ -77,8 +75,3 @@ memsynth6		CE,-S			ivltests
 memsynth7		CE,-S			ivltests
 memsynth9		CE,-S			ivltests
 mix_reset		CE,-S			ivltests
-
-# These tests pass, but synthesis is creating unnecessary latches.
-case1			normal			ivltests
-case2			normal			ivltests
-casex_synth		normal			ivltests

ivtest/regress-vvp.list

@@ -1,4 +1,26 @@
 
 # Test list files are a list of test names and the json that
 # describes the test.
+
+array_packed_write_read		vvp_tests/array_packed_write_read.json
+case1				vvp_tests/case1.json
+case2				vvp_tests/case2.json
+case2-S				vvp_tests/case2-S.json
+case3				vvp_tests/case3.json
+casex_synth			vvp_tests/casex_synth.json
+dffsynth			vvp_tests/dffsynth.json
+dffsynth-S			vvp_tests/dffsynth-S.json
+dffsynth2			vvp_tests/dffsynth2.json
+dffsynth3			vvp_tests/dffsynth3.json
+dffsynth4			vvp_tests/dffsynth4.json
+dffsynth5			vvp_tests/dffsynth5.json
+dffsynth6			vvp_tests/dffsynth6.json
+dffsynth7			vvp_tests/dffsynth7.json
+dffsynth8			vvp_tests/dffsynth8.json
+dffsynth9			vvp_tests/dffsynth9.json
+dffsynth10			vvp_tests/dffsynth10.json
+dffsynth11			vvp_tests/dffsynth11.json
 macro_str_esc			vvp_tests/macro_str_esc.json
+memsynth1			vvp_tests/memsynth1.json
+struct_packed_write_read	vvp_tests/struct_packed_write_read.json
+struct_packed_write_read2	vvp_tests/struct_packed_write_read2.json

ivtest/sv_regress.list

@@ -59,10 +59,8 @@
 # gold or diff commands.
 #
 
-struct_packed_write_read normal,-g2009   ivltests
 struct_packed_value_list normal,-g2009   ivltests
 
-array_packed_write_read  normal,-g2009   ivltests
 array_packed_value_list  normal,-g2009   ivltests
 array_packed_sysfunct    normal,-g2009   ivltests
 

ivtest/vvp_tests/array_packed_write_read.json

@@ -0,0 +1,5 @@
+{
+    "type"   : "normal",
+    "source" : "array_packed_write_read.v",
+    "iverilog-args" : [ "-g2009" ]
+}

ivtest/vvp_tests/case1.json

@@ -0,0 +1,4 @@
+{
+    "type"   : "normal",
+    "source" : "case1.v"
+}

ivtest/vvp_tests/case2.json

@@ -0,0 +1,4 @@
+{
+    "type"   : "normal",
+    "source" : "case2.v"
+}

ivtest/vvp_tests/case3.json

@@ -0,0 +1,4 @@
+{
+    "type"   : "normal",
+    "source" : "case3.v"
+}

ivtest/vvp_tests/casex_synth.json

@@ -0,0 +1,5 @@
+{
+    "type"   : "normal",
+    "source" : "casex_synth.v",
+    "iverilog-args" : [ "-S" ]
+}

ivtest/vvp_tests/dffsynth-S.json

@@ -0,0 +1,5 @@
+{
+    "type"   : "NI",
+    "source" : "dffsynth.v",
+    "iverilog-args" : [ "-S" ]
+}

ivtest/vvp_tests/dffsynth.json

@@ -0,0 +1,4 @@
+{
+    "type"   : "normal",
+    "source" : "dffsynth.v"
+}

ivtest/vvp_tests/dffsynth10.json

@@ -0,0 +1,5 @@
+{
+    "type"   : "normal",
+    "source" : "dffsynth10.v",
+    "iverilog-args" : [ "-S" ]
+}

ivtest/vvp_tests/dffsynth11.json

@@ -0,0 +1,5 @@
+{
+    "type"   : "normal",
+    "source" : "dffsynth11.v",
+    "iverilog-args" : [ "-S" ]
+}

ivtest/vvp_tests/dffsynth2.json

@@ -0,0 +1,5 @@
+{
+    "type"   : "normal",
+    "source" : "dffsynth2.v",
+    "iverilog-args" : [ "-S" ]
+}

ivtest/vvp_tests/dffsynth3.json

@@ -0,0 +1,5 @@
+{
+    "type"   : "normal",
+    "source" : "dffsynth3.v",
+    "iverilog-args" : [ "-S" ]
+}

ivtest/vvp_tests/dffsynth4.json

@@ -0,0 +1,5 @@
+{
+    "type"   : "normal",
+    "source" : "dffsynth4.v",
+    "iverilog-args" : [ "-S" ]
+}

ivtest/vvp_tests/dffsynth5.json

@@ -0,0 +1,5 @@
+{
+    "type"   : "normal",
+    "source" : "dffsynth5.v",
+    "iverilog-args" : [ "-S" ]
+}

ivtest/vvp_tests/dffsynth6.json

@@ -0,0 +1,5 @@
+{
+    "type"   : "normal",
+    "source" : "dffsynth6.v",
+    "iverilog-args" : [ "-S" ]
+}

ivtest/vvp_tests/dffsynth7.json

@@ -0,0 +1,5 @@
+{
+    "type"   : "normal",
+    "source" : "dffsynth7.v",
+    "iverilog-args" : [ "-S" ]
+}

ivtest/vvp_tests/dffsynth8.json

@@ -0,0 +1,5 @@
+{
+    "type"   : "NI",
+    "source" : "dffsynth8.v",
+    "iverilog-args" : [ "-S" ]
+}

ivtest/vvp_tests/dffsynth9.json

@@ -0,0 +1,5 @@
+{
+    "type"   : "normal",
+    "source" : "dffsynth9.v",
+    "iverilog-args" : [ "-S" ]
+}

ivtest/vvp_tests/memsynth1.json

@@ -0,0 +1,5 @@
+{
+    "type"   : "NI",
+    "source" : "memsynth1.v",
+    "iverilog-args" : [ "-S" ]
+}

ivtest/vvp_tests/struct_packed_write_read.json

@@ -0,0 +1,5 @@
+{
+    "type"   : "normal",
+    "source" : "struct_packed_write_read.v",
+    "iverilog-args" : [ "-g2009" ]
+}

ivtest/vvp_tests/struct_packed_write_read2.json

@@ -0,0 +1,5 @@
+{
+    "type"   : "normal",
+    "source" : "struct_packed_write_read2.v",
+    "iverilog-args" : [ "-g2009" ]
+}