parse more verilog.
This commit is contained in:
steve
parent
63627de7fa
commit
29da349106
11
lexor.lex
11
lexor.lex
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@ -19,7 +19,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: lexor.lex,v 1.18 1999/06/12 03:41:30 steve Exp $"
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#ident "$Id: lexor.lex,v 1.19 1999/06/12 20:35:27 steve Exp $"
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#endif
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//# define YYSTYPE lexval
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@ -57,6 +57,7 @@ static verinum*make_unsized_hex(const char*txt);
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%x CSTRING
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%s UDPTABLE
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%x PPINCLUDE
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%x PPTIMESCALE
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%%
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@ -168,6 +169,14 @@ static verinum*make_unsized_hex(const char*txt);
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delete[]bits;
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return NUMBER; }
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`timescale { BEGIN(PPTIMESCALE); }
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<PPTIMESCALE>. { ; }
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<PPTIMESCALE>\n {
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cerr << yylloc.text << ":" << yylloc.first_line
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<< ": Sorry, `timescale not supported." << endl;
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yylloc.first_line += 1;
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BEGIN(0); }
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`include {
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BEGIN(PPINCLUDE); }
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46
parse.y
46
parse.y
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@ -19,7 +19,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: parse.y,v 1.37 1999/06/12 03:42:57 steve Exp $"
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#ident "$Id: parse.y,v 1.38 1999/06/12 20:35:27 steve Exp $"
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#endif
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# include "parse_misc.h"
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@ -53,7 +53,7 @@ extern void lex_end_table();
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NetNet::PortType porttype;
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PWire*wire;
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list<PWire*>*wires;
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svector<PWire*>*wires;
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PEventStatement*event_statement;
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Statement*statement;
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@ -222,9 +222,9 @@ delay_value
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;
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delay_value_list
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: delay_value
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: expression
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{ $$ = $1; }
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| delay_value_list ',' delay_value
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| delay_value_list ',' expression
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{ yyerror(@1, "Sorry, delay value lists not supported.");
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$$ = $1;
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delete $3;
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@ -698,13 +698,13 @@ identifier
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list_of_ports
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: port
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{ list<PWire*>*tmp = new list<PWire*>;
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tmp->push_back($1);
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{ svector<PWire*>*tmp = new svector<PWire*>(1);
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(*tmp)[0] = $1;
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$$ = tmp;
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}
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| list_of_ports ',' port
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{ list<PWire*>*tmp = $1;
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tmp->push_back($3);
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{ svector<PWire*>*tmp = new svector<PWire*>(*$1, $3);
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delete $1;
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$$ = tmp;
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}
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;
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@ -1111,6 +1111,12 @@ register_variable
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{ pform_makewire(@1, *$1, NetNet::REG);
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$$ = $1;
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}
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| IDENTIFIER '=' expression
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{ pform_makewire(@1, *$1, NetNet::REG);
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yyerror(@2, "net declaration assignment to reg/integer not allowed.");
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delete $3;
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$$ = $1;
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}
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| IDENTIFIER '[' expression ':' expression ']'
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{ pform_makewire(@1, *$1, NetNet::REG);
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if (! pform_expression_is_constant($3))
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@ -1175,9 +1181,21 @@ statement
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| K_disable IDENTIFIER ';'
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{ yyerror(@1, "Sorry, disable statements not supported.");
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delete $2;
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$$ = 0;
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}
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| K_forever statement
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{ yyerror(@1, "Sorry, forever statements not supported.");
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delete $2;
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$$ = 0;
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}
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| K_fork statement_list K_join
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{ $$ = pform_make_block(PBlock::BL_PAR, $2); }
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| K_repeat '(' expression ')' statement
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{ yyerror(@1, "Sorry, repeat statements not supported.");
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delete $3;
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delete $5;
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$$ = 0;
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}
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| K_begin K_end
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{ $$ = pform_make_block(PBlock::BL_SEQ, 0); }
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| K_begin ':' IDENTIFIER K_end
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@ -1479,16 +1497,16 @@ udp_port_decl
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| K_output IDENTIFIER ';'
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{ PWire*pp = new PWire(*$2);
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pp->port_type = NetNet::POUTPUT;
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list<PWire*>*tmp = new list<PWire*>;
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tmp->push_back(pp);
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svector<PWire*>*tmp = new svector<PWire*>(1);
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(*tmp)[0] = pp;
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delete $2;
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$$ = tmp;
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}
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| K_reg IDENTIFIER ';'
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{ PWire*pp = new PWire(*$2, NetNet::REG);
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pp->port_type = NetNet::PIMPLICIT;
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list<PWire*>*tmp = new list<PWire*>;
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tmp->push_back(pp);
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svector<PWire*>*tmp = new svector<PWire*>(1);
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(*tmp)[0] = pp;
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delete $2;
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$$ = tmp;
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}
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@ -1498,8 +1516,8 @@ udp_port_decls
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: udp_port_decl
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{ $$ = $1; }
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| udp_port_decls udp_port_decl
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{ list<PWire*>*tmp = $1;
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tmp->merge(*$2);
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{ svector<PWire*>*tmp = new svector<PWire*>(*$1, *$2);
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delete $1;
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delete $2;
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$$ = tmp;
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}
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60
pform.cc
60
pform.cc
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: pform.cc,v 1.24 1999/06/12 03:42:17 steve Exp $"
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#ident "$Id: pform.cc,v 1.25 1999/06/12 20:35:27 steve Exp $"
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#endif
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# include "compiler.h"
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@ -57,20 +57,16 @@ static unsigned long evaluate_delay(PExpr*delay)
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return pp->value().as_ulong();
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}
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void pform_startmodule(const string&name, list<PWire*>*ports)
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void pform_startmodule(const string&name, svector<PWire*>*ports)
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{
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assert( cur_module == 0 );
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cur_module = new Module(name, ports? ports->size() : 0);
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cur_module = new Module(name, ports? ports->count() : 0);
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if (ports) {
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unsigned idx = 0;
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for (list<PWire*>::iterator cur = ports->begin()
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; cur != ports->end()
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; cur ++ ) {
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cur_module->add_wire(*cur);
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cur_module->ports[idx++] = *cur;
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for (unsigned idx = 0 ; idx < ports->count() ; idx += 1) {
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cur_module->add_wire((*ports)[idx]);
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cur_module->ports[idx] = (*ports)[idx];
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}
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delete ports;
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}
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}
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@ -89,7 +85,7 @@ bool pform_expression_is_constant(const PExpr*ex)
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}
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void pform_make_udp(string*name, list<string>*parms,
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list<PWire*>*decl, list<string>*table,
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svector<PWire*>*decl, list<string>*table,
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Statement*init_expr)
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{
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assert(parms->size() > 0);
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@ -98,28 +94,26 @@ void pform_make_udp(string*name, list<string>*parms,
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off with the parameters in the list. I will rebuild a list
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of parameters for the PUdp object. */
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map<string,PWire*> defs;
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for (list<PWire*>::iterator cur = decl->begin()
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; cur != decl->end()
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; cur ++ )
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for (unsigned idx = 0 ; idx < decl->count() ; idx += 1)
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if (defs[(*cur)->name] == 0) {
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defs[(*cur)->name] = *cur;
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if (defs[(*decl)[idx]->name] == 0) {
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defs[(*decl)[idx]->name] = (*decl)[idx];
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} else switch ((*cur)->port_type) {
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} else switch ((*decl)[idx]->port_type) {
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case NetNet::PIMPLICIT:
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case NetNet::POUTPUT:
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assert(defs[(*cur)->name]->port_type != NetNet::PINPUT);
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assert(defs[(*decl)[idx]->name]->port_type != NetNet::PINPUT);
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// OK, merge the output definitions.
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defs[(*cur)->name]->port_type = NetNet::POUTPUT;
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if ((*cur)->type == NetNet::REG)
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defs[(*cur)->name]->type = NetNet::REG;
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defs[(*decl)[idx]->name]->port_type = NetNet::POUTPUT;
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if ((*decl)[idx]->type == NetNet::REG)
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defs[(*decl)[idx]->name]->type = NetNet::REG;
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break;
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case NetNet::PINPUT:
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// Allow duplicate input declarations.
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assert(defs[(*cur)->name]->port_type == NetNet::PINPUT);
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delete *cur;
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assert(defs[(*decl)[idx]->name]->port_type == NetNet::PINPUT);
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delete (*decl)[idx];
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break;
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default:
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@ -453,8 +447,14 @@ static void pform_set_net_range(const string&name, const svector<PExpr*>*range)
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cur->msb = (*range)[0];
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cur->lsb = (*range)[1];
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} else {
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assert(cur->msb);
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assert(cur->lsb);
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if (cur->msb == 0) {
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VLerror(yylloc, "missing msb of range.");
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return;
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}
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if (cur->lsb == 0) {
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VLerror(yylloc, "missing lsb of range.");
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return;
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}
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PExpr*msb = (*range)[0];
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PExpr*lsb = (*range)[1];
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assert(msb);
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@ -519,16 +519,17 @@ void pform_set_reg_integer(list<string>*names)
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}
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}
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list<PWire*>* pform_make_udp_input_ports(list<string>*names)
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svector<PWire*>* pform_make_udp_input_ports(list<string>*names)
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{
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list<PWire*>*out = new list<PWire*>;
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svector<PWire*>*out = new svector<PWire*>(names->size());
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unsigned idx = 0;
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for (list<string>::const_iterator cur = names->begin()
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; cur != names->end()
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; cur ++ ) {
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PWire*pp = new PWire(*cur);
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pp->port_type = NetNet::PINPUT;
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out->push_back(pp);
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(*out)[idx] = pp;
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}
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delete names;
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@ -589,6 +590,9 @@ int pform_parse(const char*path, map<string,Module*>&modules,
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/*
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* $Log: pform.cc,v $
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* Revision 1.25 1999/06/12 20:35:27 steve
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* parse more verilog.
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*
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* Revision 1.24 1999/06/12 03:42:17 steve
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* Assert state of bit range expressions.
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*
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11
pform.h
11
pform.h
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@ -19,7 +19,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: pform.h,v 1.18 1999/06/06 20:45:39 steve Exp $"
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#ident "$Id: pform.h,v 1.19 1999/06/12 20:35:27 steve Exp $"
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#endif
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# include "netlist.h"
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@ -95,11 +95,11 @@ struct lgate {
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* are to apply to the scope of that module. The endmodule causes the
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* pform to close up and finish the named module.
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*/
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extern void pform_startmodule(const string&, list<PWire*>*ports);
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extern void pform_startmodule(const string&, svector<PWire*>*ports);
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extern void pform_endmodule(const string&);
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extern void pform_make_udp(string*name, list<string>*parms,
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list<PWire*>*decl, list<string>*table,
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svector<PWire*>*decl, list<string>*table,
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Statement*init);
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/*
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@ -123,7 +123,7 @@ extern PProcess* pform_make_behavior(PProcess::Type, Statement*);
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extern Statement* pform_make_block(PBlock::BL_TYPE, list<Statement*>*);
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extern Statement* pform_make_calltask(string*t, svector<PExpr*>* =0);
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extern list<PWire*>* pform_make_udp_input_ports(list<string>*);
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extern svector<PWire*>* pform_make_udp_input_ports(list<string>*);
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extern bool pform_expression_is_constant(const PExpr*);
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@ -152,6 +152,9 @@ extern void pform_dump(ostream&out, Module*mod);
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/*
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* $Log: pform.h,v $
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* Revision 1.19 1999/06/12 20:35:27 steve
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* parse more verilog.
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*
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* Revision 1.18 1999/06/06 20:45:39 steve
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* Add parse and elaboration of non-blocking assignments,
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* Replace list<PCase::Item*> with an svector version,
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