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iverilog
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parse more verilog.

This commit is contained in:
steve 1999-06-12 20:35:27 +00:00
parent 63627de7fa
commit 29da349106
4 changed files with 81 additions and 47 deletions
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11
lexor.lex
View File

@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) #if !defined(WINNT)
#ident "$Id: lexor.lex,v 1.18 1999/06/12 03:41:30 steve Exp $" #ident "$Id: lexor.lex,v 1.19 1999/06/12 20:35:27 steve Exp $"
#endif #endif
//# define YYSTYPE lexval //# define YYSTYPE lexval
@ -57,6 +57,7 @@ static verinum*make_unsized_hex(const char*txt);
%x CSTRING %x CSTRING
%s UDPTABLE %s UDPTABLE
%x PPINCLUDE %x PPINCLUDE
%x PPTIMESCALE
%% %%
@ -168,6 +169,14 @@ static verinum*make_unsized_hex(const char*txt);
delete[]bits; delete[]bits;
return NUMBER; } return NUMBER; }
`timescale { BEGIN(PPTIMESCALE); }
<PPTIMESCALE>. { ; }
<PPTIMESCALE>\n {
cerr << yylloc.text << ":" << yylloc.first_line
<< ": Sorry, `timescale not supported." << endl;
yylloc.first_line += 1;
BEGIN(0); }
`include { `include {
BEGIN(PPINCLUDE); } BEGIN(PPINCLUDE); }

46
parse.y
View File

@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) #if !defined(WINNT)
#ident "$Id: parse.y,v 1.37 1999/06/12 03:42:57 steve Exp $" #ident "$Id: parse.y,v 1.38 1999/06/12 20:35:27 steve Exp $"
#endif #endif
# include "parse_misc.h" # include "parse_misc.h"
@ -53,7 +53,7 @@ extern void lex_end_table();
NetNet::PortType porttype; NetNet::PortType porttype;
PWire*wire; PWire*wire;
list<PWire*>*wires; svector<PWire*>*wires;
PEventStatement*event_statement; PEventStatement*event_statement;
Statement*statement; Statement*statement;
@ -222,9 +222,9 @@ delay_value
; ;
delay_value_list delay_value_list
: delay_value : expression
{ $$ = $1; } { $$ = $1; }
| delay_value_list ',' delay_value | delay_value_list ',' expression
{ yyerror(@1, "Sorry, delay value lists not supported."); { yyerror(@1, "Sorry, delay value lists not supported.");
$$ = $1; $$ = $1;
delete $3; delete $3;
@ -698,13 +698,13 @@ identifier
list_of_ports list_of_ports
: port : port
{ list<PWire*>*tmp = new list<PWire*>; { svector<PWire*>*tmp = new svector<PWire*>(1);
tmp->push_back($1); (*tmp)[0] = $1;
$$ = tmp; $$ = tmp;
} }
| list_of_ports ',' port | list_of_ports ',' port
{ list<PWire*>*tmp = $1; { svector<PWire*>*tmp = new svector<PWire*>(*$1, $3);
tmp->push_back($3); delete $1;
$$ = tmp; $$ = tmp;
} }
; ;
@ -1111,6 +1111,12 @@ register_variable
{ pform_makewire(@1, *$1, NetNet::REG); { pform_makewire(@1, *$1, NetNet::REG);
$$ = $1; $$ = $1;
} }
| IDENTIFIER '=' expression
{ pform_makewire(@1, *$1, NetNet::REG);
yyerror(@2, "net declaration assignment to reg/integer not allowed.");
delete $3;
$$ = $1;
}
| IDENTIFIER '[' expression ':' expression ']' | IDENTIFIER '[' expression ':' expression ']'
{ pform_makewire(@1, *$1, NetNet::REG); { pform_makewire(@1, *$1, NetNet::REG);
if (! pform_expression_is_constant($3)) if (! pform_expression_is_constant($3))
@ -1175,9 +1181,21 @@ statement
| K_disable IDENTIFIER ';' | K_disable IDENTIFIER ';'
{ yyerror(@1, "Sorry, disable statements not supported."); { yyerror(@1, "Sorry, disable statements not supported.");
delete $2; delete $2;
$$ = 0;
}
| K_forever statement
{ yyerror(@1, "Sorry, forever statements not supported.");
delete $2;
$$ = 0;
} }
| K_fork statement_list K_join | K_fork statement_list K_join
{ $$ = pform_make_block(PBlock::BL_PAR, $2); } { $$ = pform_make_block(PBlock::BL_PAR, $2); }
| K_repeat '(' expression ')' statement
{ yyerror(@1, "Sorry, repeat statements not supported.");
delete $3;
delete $5;
$$ = 0;
}
| K_begin K_end | K_begin K_end
{ $$ = pform_make_block(PBlock::BL_SEQ, 0); } { $$ = pform_make_block(PBlock::BL_SEQ, 0); }
| K_begin ':' IDENTIFIER K_end | K_begin ':' IDENTIFIER K_end
@ -1479,16 +1497,16 @@ udp_port_decl
| K_output IDENTIFIER ';' | K_output IDENTIFIER ';'
{ PWire*pp = new PWire(*$2); { PWire*pp = new PWire(*$2);
pp->port_type = NetNet::POUTPUT; pp->port_type = NetNet::POUTPUT;
list<PWire*>*tmp = new list<PWire*>; svector<PWire*>*tmp = new svector<PWire*>(1);
tmp->push_back(pp); (*tmp)[0] = pp;
delete $2; delete $2;
$$ = tmp; $$ = tmp;
} }
| K_reg IDENTIFIER ';' | K_reg IDENTIFIER ';'
{ PWire*pp = new PWire(*$2, NetNet::REG); { PWire*pp = new PWire(*$2, NetNet::REG);
pp->port_type = NetNet::PIMPLICIT; pp->port_type = NetNet::PIMPLICIT;
list<PWire*>*tmp = new list<PWire*>; svector<PWire*>*tmp = new svector<PWire*>(1);
tmp->push_back(pp); (*tmp)[0] = pp;
delete $2; delete $2;
$$ = tmp; $$ = tmp;
} }
@ -1498,8 +1516,8 @@ udp_port_decls
: udp_port_decl : udp_port_decl
{ $$ = $1; } { $$ = $1; }
| udp_port_decls udp_port_decl | udp_port_decls udp_port_decl
{ list<PWire*>*tmp = $1; { svector<PWire*>*tmp = new svector<PWire*>(*$1, *$2);
tmp->merge(*$2); delete $1;
delete $2; delete $2;
$$ = tmp; $$ = tmp;
} }

60
pform.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) #if !defined(WINNT)
#ident "$Id: pform.cc,v 1.24 1999/06/12 03:42:17 steve Exp $" #ident "$Id: pform.cc,v 1.25 1999/06/12 20:35:27 steve Exp $"
#endif #endif
# include "compiler.h" # include "compiler.h"
@ -57,20 +57,16 @@ static unsigned long evaluate_delay(PExpr*delay)
return pp->value().as_ulong(); return pp->value().as_ulong();
} }
void pform_startmodule(const string&name, list<PWire*>*ports) void pform_startmodule(const string&name, svector<PWire*>*ports)
{ {
assert( cur_module == 0 ); assert( cur_module == 0 );
cur_module = new Module(name, ports? ports->size() : 0); cur_module = new Module(name, ports? ports->count() : 0);
if (ports) { if (ports) {
unsigned idx = 0; for (unsigned idx = 0 ; idx < ports->count() ; idx += 1) {
for (list<PWire*>::iterator cur = ports->begin() cur_module->add_wire((*ports)[idx]);
; cur != ports->end() cur_module->ports[idx] = (*ports)[idx];
; cur ++ ) {
cur_module->add_wire(*cur);
cur_module->ports[idx++] = *cur;
} }
delete ports; delete ports;
} }
} }
@ -89,7 +85,7 @@ bool pform_expression_is_constant(const PExpr*ex)
} }
void pform_make_udp(string*name, list<string>*parms, void pform_make_udp(string*name, list<string>*parms,
list<PWire*>*decl, list<string>*table, svector<PWire*>*decl, list<string>*table,
Statement*init_expr) Statement*init_expr)
{ {
assert(parms->size() > 0); assert(parms->size() > 0);
@ -98,28 +94,26 @@ void pform_make_udp(string*name, list<string>*parms,
off with the parameters in the list. I will rebuild a list off with the parameters in the list. I will rebuild a list
of parameters for the PUdp object. */ of parameters for the PUdp object. */
map<string,PWire*> defs; map<string,PWire*> defs;
for (list<PWire*>::iterator cur = decl->begin() for (unsigned idx = 0 ; idx < decl->count() ; idx += 1)
; cur != decl->end()
; cur ++ )
if (defs[(*cur)->name] == 0) { if (defs[(*decl)[idx]->name] == 0) {
defs[(*cur)->name] = *cur; defs[(*decl)[idx]->name] = (*decl)[idx];
} else switch ((*cur)->port_type) { } else switch ((*decl)[idx]->port_type) {
case NetNet::PIMPLICIT: case NetNet::PIMPLICIT:
case NetNet::POUTPUT: case NetNet::POUTPUT:
assert(defs[(*cur)->name]->port_type != NetNet::PINPUT); assert(defs[(*decl)[idx]->name]->port_type != NetNet::PINPUT);
// OK, merge the output definitions. // OK, merge the output definitions.
defs[(*cur)->name]->port_type = NetNet::POUTPUT; defs[(*decl)[idx]->name]->port_type = NetNet::POUTPUT;
if ((*cur)->type == NetNet::REG) if ((*decl)[idx]->type == NetNet::REG)
defs[(*cur)->name]->type = NetNet::REG; defs[(*decl)[idx]->name]->type = NetNet::REG;
break; break;
case NetNet::PINPUT: case NetNet::PINPUT:
// Allow duplicate input declarations. // Allow duplicate input declarations.
assert(defs[(*cur)->name]->port_type == NetNet::PINPUT); assert(defs[(*decl)[idx]->name]->port_type == NetNet::PINPUT);
delete *cur; delete (*decl)[idx];
break; break;
default: default:
@ -453,8 +447,14 @@ static void pform_set_net_range(const string&name, const svector<PExpr*>*range)
cur->msb = (*range)[0]; cur->msb = (*range)[0];
cur->lsb = (*range)[1]; cur->lsb = (*range)[1];
} else { } else {
assert(cur->msb); if (cur->msb == 0) {
assert(cur->lsb); VLerror(yylloc, "missing msb of range.");
return;
}
if (cur->lsb == 0) {
VLerror(yylloc, "missing lsb of range.");
return;
}
PExpr*msb = (*range)[0]; PExpr*msb = (*range)[0];
PExpr*lsb = (*range)[1]; PExpr*lsb = (*range)[1];
assert(msb); assert(msb);
@ -519,16 +519,17 @@ void pform_set_reg_integer(list<string>*names)
} }
} }
list<PWire*>* pform_make_udp_input_ports(list<string>*names) svector<PWire*>* pform_make_udp_input_ports(list<string>*names)
{ {
list<PWire*>*out = new list<PWire*>; svector<PWire*>*out = new svector<PWire*>(names->size());
unsigned idx = 0;
for (list<string>::const_iterator cur = names->begin() for (list<string>::const_iterator cur = names->begin()
; cur != names->end() ; cur != names->end()
; cur ++ ) { ; cur ++ ) {
PWire*pp = new PWire(*cur); PWire*pp = new PWire(*cur);
pp->port_type = NetNet::PINPUT; pp->port_type = NetNet::PINPUT;
out->push_back(pp); (*out)[idx] = pp;
} }
delete names; delete names;
@ -589,6 +590,9 @@ int pform_parse(const char*path, map<string,Module*>&modules,
/* /*
* $Log: pform.cc,v $ * $Log: pform.cc,v $
* Revision 1.25 1999/06/12 20:35:27 steve
* parse more verilog.
*
* Revision 1.24 1999/06/12 03:42:17 steve * Revision 1.24 1999/06/12 03:42:17 steve
* Assert state of bit range expressions. * Assert state of bit range expressions.
* *

11
pform.h
View File

@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) #if !defined(WINNT)
#ident "$Id: pform.h,v 1.18 1999/06/06 20:45:39 steve Exp $" #ident "$Id: pform.h,v 1.19 1999/06/12 20:35:27 steve Exp $"
#endif #endif
# include "netlist.h" # include "netlist.h"
@ -95,11 +95,11 @@ struct lgate {
* are to apply to the scope of that module. The endmodule causes the * are to apply to the scope of that module. The endmodule causes the
* pform to close up and finish the named module. * pform to close up and finish the named module.
*/ */
extern void pform_startmodule(const string&, list<PWire*>*ports); extern void pform_startmodule(const string&, svector<PWire*>*ports);
extern void pform_endmodule(const string&); extern void pform_endmodule(const string&);
extern void pform_make_udp(string*name, list<string>*parms, extern void pform_make_udp(string*name, list<string>*parms,
list<PWire*>*decl, list<string>*table, svector<PWire*>*decl, list<string>*table,
Statement*init); Statement*init);
/* /*
@ -123,7 +123,7 @@ extern PProcess* pform_make_behavior(PProcess::Type, Statement*);
extern Statement* pform_make_block(PBlock::BL_TYPE, list<Statement*>*); extern Statement* pform_make_block(PBlock::BL_TYPE, list<Statement*>*);
extern Statement* pform_make_calltask(string*t, svector<PExpr*>* =0); extern Statement* pform_make_calltask(string*t, svector<PExpr*>* =0);
extern list<PWire*>* pform_make_udp_input_ports(list<string>*); extern svector<PWire*>* pform_make_udp_input_ports(list<string>*);
extern bool pform_expression_is_constant(const PExpr*); extern bool pform_expression_is_constant(const PExpr*);
@ -152,6 +152,9 @@ extern void pform_dump(ostream&out, Module*mod);
/* /*
* $Log: pform.h,v $ * $Log: pform.h,v $
* Revision 1.19 1999/06/12 20:35:27 steve
* parse more verilog.
*
* Revision 1.18 1999/06/06 20:45:39 steve * Revision 1.18 1999/06/06 20:45:39 steve
* Add parse and elaboration of non-blocking assignments, * Add parse and elaboration of non-blocking assignments,
* Replace list<PCase::Item*> with an svector version, * Replace list<PCase::Item*> with an svector version,