Support writing some XNF things into an NCF file.

t-xnf.cc

@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT)
-#ident "$Id: t-xnf.cc,v 1.14 1999/11/05 18:43:12 steve Exp $"
+#ident "$Id: t-xnf.cc,v 1.15 1999/11/06 04:51:42 steve Exp $"
 #endif
 
 /* XNF BACKEND
@@ -33,6 +33,12 @@
  *	PART record. Valid types are defined by Xilinx or the
  *	receiving tools.
  *
+ *   ncf=<path>
+ *      Specify the path to a NCF file. This is an OUTPUT file into
+ *      which the code generator will write netlist constraints that
+ *      relate to pin assignments, CLB placement, etc. If this flag is
+ *      not given, no NCF file will be written.
+ *
  * WIRE ATTRIBUTES
  *
  *   PAD = <io><n>
@@ -63,6 +69,7 @@
 
 # include  "netlist.h"
 # include  "target.h"
+# include  <fstream>
 
 class target_xnf  : public target_t {
 
@@ -86,6 +93,8 @@ class target_xnf  : public target_t {
 			   const NetObj::Link&lnk);
       static void draw_sym_with_lcaname(ostream&os, string lca,
 					const NetNode*net);
+
+      ofstream ncf_;
 };
 
 /*
@@ -181,15 +190,24 @@ void target_xnf::draw_sym_with_lcaname(ostream&os, string lca,
 
 void target_xnf::start_design(ostream&os, const Design*des)
 {
+      string ncfpath = des->get_flag("ncf");
+      if (ncfpath != "")
+	    ncf_.open(ncfpath.c_str());
+
       os << "LCANET,6" << endl;
       os << "PROG,verilog,0.2PRE,\"Icarus Verilog\"" << endl;
-      if (des->get_flag("part") != "")
+      ncf_ << "# Generated by Icarus Verilog 0.2PRE" << endl;
+
+      if (des->get_flag("part") != "") {
 	    os << "PART," << des->get_flag("part") << endl;
+	    ncf_ << "CONFIG PART=" << des->get_flag("part") << ";" << endl;
+      }
 }
 
 void target_xnf::end_design(ostream&os, const Design*)
 {
       os << "EOF" << endl;
+      ncf_.close();
 }
 
 void scrape_pad_info(string str, char&dir, unsigned&num)
@@ -259,6 +277,12 @@ void target_xnf::signal(ostream&os, const NetNet*net)
       scrape_pad_info(pad, dir, num);
       os << "EXT, " << mangle(net->name()) << ", " << dir
 	 << ", " << num << endl;
+
+      ncf_ << "# Assignment to pin " << num << " (DIR=" << dir <<
+	    ") by $attribute(" << net->name() << ", \"PAD\", \"" <<
+	    pad << "\")" << endl;
+      ncf_ << "NET " << mangle(net->name()) << " LOC=P" << num << ";"
+	   << endl;
 }
 
 /*
@@ -307,7 +331,7 @@ void target_xnf::lpm_add_sub(ostream&os, const NetAddSub*gate)
       os << "END" << endl;
 
 	/* Now make the 2 bit adders that chain from the cin
-	   initializer and up. Safe the tail bit (if there is one) for
+	   initializer and up. Save the tail bit (if there is one) for
 	   later. */
       for (unsigned idx = 0 ;  idx < (width&~1) ;  idx += 2) {
 	    os << "SYM, " << name_cy4 << "<" << idx << ">, CY4, "
@@ -591,6 +615,9 @@ extern const struct target tgt_xnf = { "xnf", &target_xnf_obj };
 
 /*
  * $Log: t-xnf.cc,v $
+ * Revision 1.15  1999/11/06 04:51:42  steve
+ *  Support writing some XNF things into an NCF file.
+ *
  * Revision 1.14  1999/11/05 18:43:12  steve
  *  fix syntax of EQN record.
  *

xnf.txt

@@ -15,11 +15,12 @@ GENERATE XNF OUTPUT -- THE SHORT STORY
 The easiest way to compile for XNF output is with the "verilog"
 command (man verilog) and the -X switch:
 
-	% verilog -fpart=4010e -X prog.v
+	% verilog -fpart=4010e -fncf=prog.ncf -X prog.v
 
-This generates from the prog.v Verilog source file the prog.xnf
+This generates from the prog.v Verilog source file the prog.xnf output
-output. The verilog program arranges to call the preprocessor and the
+and the prog.ncf netlist constraints file. The verilog program
-ivl compiler with all the correct switches for generating XNF.
+arranges to call the preprocessor and the ivl compiler with all the
+correct switches for generating XNF.
 
 XNF PADS IN VERILOG SOURCE
 
@@ -109,6 +110,19 @@ generated. The ``synth'' function matches certain behavioral constructs
 to structural components, and the xnfio function generates pads and
 fills the IOBs.
 
+SUPPORTED FLAGS
+
+    -fpart=<part>
+        Specify the type of part to target. This string is written
+        literally into the PART, record of the XNF, and may also be
+        used to control synthesis and placement.
+
+    -fncf=<path>
+        Cause the code generator to write into <path> the netlist
+        constraints needed for controlling placement and timing. This
+        switch is required if pin assignments are assigned in the
+        Verilog source.
+
 THE SYNTH FUNCTION
 
 This function does synthesis transformations on the entered design,
@@ -162,6 +176,9 @@ IBUF, NOT gates cannot be absorbed as in the OPAD case.
 
 
  $Log: xnf.txt,v $
+ Revision 1.8  1999/11/06 04:51:42  steve
+  Support writing some XNF things into an NCF file.
+
  Revision 1.7  1999/11/03 05:18:18  steve
   XNF synthesis now uses the synth functor.