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Merge branch 'master' of steve-icarus@icarus.com:git/verilog

This commit is contained in:
Stephen Williams 2007-08-13 19:58:56 -07:00
parent 632685d830 9b807c78d3
commit 268e2df011
1 changed files with 4 additions and 4 deletions
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verilog.spec
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@ -1,14 +1,14 @@
Summary: Icarus Verilog Summary: Icarus Verilog
Name: verilog Name: verilog
Version: 0.9.0.20070608 Version: 0.9.0.20070812
Release: 0 Release: 0
License: GPL License: GPL
Group: Productivity/Scientific/Electronics Group: Productivity/Scientific/Electronics
Source: verilog-20070608.tar.gz Source: verilog-20070812.tar.gz
URL: http://www.icarus.com/eda/verilog/index.html URL: http://www.icarus.com/eda/verilog/index.html
Packager: Stephen Williams <steve@icarus.com> Packager: Stephen Williams <steve@icarus.com>
BuildRoot: %{_tmppath}/%{name}-%{version}-20070608-%{release}-root BuildRoot: %{_tmppath}/%{name}-%{version}-20070812-%{release}-root
BuildRequires: gcc-c++, zlib-devel, bison, flex, gperf, readline-devel BuildRequires: gcc-c++, zlib-devel, bison, flex, gperf, readline-devel
@ -32,7 +32,7 @@ engineering formats, including simulation. It strives to be true
to the IEEE-1364 standard. to the IEEE-1364 standard.
%prep %prep
%setup -n verilog-20070608 %setup -n verilog-20070812
%build %build
%ifarch x86_64 %ifarch x86_64