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iverilog
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support the -t switch.

This commit is contained in:
steve 1999-10-08 03:57:19 +00:00
parent 6997971884
commit 213d02c4e5
1 changed files with 19 additions and 14 deletions
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27
verilog.sh
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@ -17,6 +17,7 @@
# along with this program; if not, write to the Free Software # along with this program; if not, write to the Free Software
# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
# Added support for the -t flag, for odd-ball target types. <steve@icarus.com>
# Setup variables # Setup variables
execPath=@bindir@ execPath=@bindir@
@ -24,16 +25,13 @@ execIVLPP=${execPath}/ivlpp
execIVL=${execPath}/ivl execIVL=${execPath}/ivl
execCpp=/usr/bin/g++ execCpp=/usr/bin/g++
vvmTarget="-t vvm"
xnfTarget="-t xnf"
tmpDir=/tmp tmpDir=/tmp
tmpPPFile=${tmpDir}/ivl$$.pp tmpPPFile=${tmpDir}/ivl$$.pp
tmpCCFile=${tmpDir}/ivl$$.cc tmpCCFile=${tmpDir}/ivl$$.cc
VPIModulePath=@libdir@/ivl:. VPIModulePath=@libdir@/ivl:.
target=${vvmTarget} target="vvm"
targetSuffix="" targetSuffix=""
# If VPI module path aren't set up, warn at least # If VPI module path aren't set up, warn at least
@ -43,16 +41,17 @@ if test -z "${VPI_MODULE_PATH}" ; then
fi fi
# Try to extract given parameters # Try to extract given parameters
parameter=`getopt D:I:Xxo:s: "$@"` parameter=`getopt D:I:Xxo:s:t: "$@"`
eval set -- "${parameter}" eval set -- "${parameter}"
while true ; do while true ; do
case "$1" in case "$1" in
-D) extDefines="${extDefines} -D$2" ; shift 2 ;; -D) extDefines="${extDefines} -D$2" ; shift 2 ;;
-I) extIncPath="${extIncPath} -I $2" ; shift 2 ;; -I) extIncPath="${extIncPath} -I $2" ; shift 2 ;;
-X) targetSuffix=".xnf" ; target=${xnfTarget} ; shift ;; -X) target="xnf" ; shift ;;
-o) outputFile=$2 ; shift 2 ;; -o) outputFile=$2 ; shift 2 ;;
-s) topModule="-s $2 " ; shift 2 ;; -s) topModule="-s $2 " ; shift 2 ;;
-t) target="-t $2" ; shift 2 ;;
-x) execute="true"; shift ;; -x) execute="true"; shift ;;
--) shift ; break ;; --) shift ; break ;;
*) echo "Internal error! Arg is $1 " ; exit 1 ;; *) echo "Internal error! Arg is $1 " ; exit 1 ;;
@ -69,6 +68,12 @@ if test -z "${verilogFile}" ; then
exit 1; exit 1;
fi fi
# Shoose a target file suffix based on the target type.
case "$target" in
vvm) targetSuffix="" ;;
*) targetSuffix=".$target" ;;
esac
# If no output file is given should we guess one or...? # If no output file is given should we guess one or...?
# Assumes a few silly things if several files are given # Assumes a few silly things if several files are given
@ -87,7 +92,7 @@ fi
# Compile preprocessed verilog file # Compile preprocessed verilog file
${execIVL} ${target} -o ${tmpCCFile} ${topModule} ${tmpPPFile} ${execIVL} -t ${target} -o ${tmpCCFile} ${topModule} ${tmpPPFile}
if test $? -ne 0 ; then if test $? -ne 0 ; then
echo "Verilog compilation failed. Terminating compilation." echo "Verilog compilation failed. Terminating compilation."
rm -f ${tmpCCFile} rm -f ${tmpCCFile}
@ -96,11 +101,11 @@ fi
rm -f ${tmpPPFile} rm -f ${tmpPPFile}
case "${targetSuffix}" in case "${target}" in
.xnf) mv ${tmpCCFile} ${outputFile} ;; "xnf") mv ${tmpCCFile} ${outputFile} ;;
"") ${execCpp} -rdynamic ${tmpCCFile} -o ${outputFile} -lvvm -ldl ; "vvm") ${execCpp} -rdynamic ${tmpCCFile} -o ${outputFile} -lvvm -ldl ;
if test $? -ne 0 ; then if test $? -ne 0 ; then
echo "C++ compilation failed. Terminating compilation." echo "C++ compilation failed. Terminating compilation."
rm -f ${tmpCCFile} rm -f ${tmpCCFile}
@ -108,7 +113,7 @@ case "${targetSuffix}" in
fi fi
rm -f ${tmpCCFile} ;; rm -f ${tmpCCFile} ;;
*) echo "Internal error in target compilation." ; exit 1 *) mv ${tmpCCFile} ${outputFile} ;;
esac esac