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iverilog
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Fix space issues in a couple files

This commit is contained in:
Cary R 2018-11-13 21:57:08 -08:00
parent 3612076943
commit 172d7eb0a3
2 changed files with 3 additions and 3 deletions
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4
README.txt
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@ -77,12 +77,12 @@ the configure scripts.
Unpack the tar-ball and cd into the verilog-######### directory Unpack the tar-ball and cd into the verilog-######### directory
(presumably that is how you got to this README) and compile the source (presumably that is how you got to this README) and compile the source
with the commands: with the commands:
./configure ./configure
make make
If you are building from git, you have to run the command below before If you are building from git, you have to run the command below before
compile the source. This will generate the "configure" file, which is compile the source. This will generate the "configure" file, which is
automatically done when building from tarball. automatically done when building from tarball.
sh autoconf.sh sh autoconf.sh

2
tgt-vhdl/stmt.cc
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@ -1250,7 +1250,7 @@ static void process_number(vhdl_binop_expr *all, vhdl_var_ref *test,
switch (bits[i]) { switch (bits[i]) {
case 'x': case 'x':
if (is_casez) break; if (is_casez) break;
// fallthrough // fallthrough
case '?': case '?':
case 'z': case 'z':
continue; // Ignore these. continue; // Ignore these.