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Soft treating of multiple architectures in VHDL 

In VHDL it is allowed to have multiple architectures
per one entity. The proper architecture should be then
chosen in a configuration block. Now, if many architectures
will be found, then there will be a warning message printed.
FIXME notes are added in order not to forget about changes to
be done
This commit is contained in:
Pawel Szostek 2011-03-23 10:27:32 +01:00 committed by Stephen Williams
parent 48dc977630
commit 13519ab5c7
2 changed files with 10 additions and 8 deletions
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11
vhdlpp/entity_elaborate.cc
View File

@ -56,20 +56,21 @@ int Entity::elaborate()
return 1; return 1;
} }
/* FIXME: the architecture for the entity should be chosen in configuration
block (not yet implemented). Multiple architectures are allowed in general */
if (arch_.size() > 1) { if (arch_.size() > 1) {
cerr << get_fileline() << ": sorry: " cerr << get_fileline() << ": sorry: "
<< "Too many architectures for entity " << get_name() << "Multiple architectures for an entity are not yet supported"
<< ". Architectures are:" << endl; << ". Architectures for entity " << get_name() << " are:" << endl;
for (map<perm_string,Architecture*>::const_iterator cur = arch_.begin() for (map<perm_string,Architecture*>::const_iterator cur = arch_.begin()
; cur != arch_.end() ; ++cur) { ; cur != arch_.end() ; ++cur) {
cerr << get_fileline() << ": : " << cur->first cerr << get_fileline() << ": : " << cur->first
<< " at " << cur->second->get_fileline() << endl; << " at " << cur->second->get_fileline() << endl;
} }
errors += 1; //errors += 1;
} }
/* FIXME: here we should look at configuration block */
bind_arch_ = arch_.begin()->second; bind_arch_ = arch_.begin()->second;
if (verbose_flag) if (verbose_flag)
cerr << "For entity " << get_name() cerr << "For entity " << get_name()

7
vhdlpp/parse_misc.cc
View File

@ -42,14 +42,15 @@ void bind_architecture_to_entity(const char*ename, Architecture*arch)
return; return;
} }
/* FIXME: entities can have multiple architectures attached to them
This is to be configured by VHDL's configurations (not yet implemented) */
Architecture*old_arch = idx->second->add_architecture(arch); Architecture*old_arch = idx->second->add_architecture(arch);
if (old_arch != arch) { if (old_arch != arch) {
cerr << arch->get_fileline() << ": error: " cerr << arch->get_fileline() << ": warning: "
<< "Architecture " << arch->get_name() << "Architecture " << arch->get_name()
<< " for entity " << idx->second->get_name() << " for entity " << idx->first
<< " is already defined here: " << old_arch->get_fileline() << endl; << " is already defined here: " << old_arch->get_fileline() << endl;
parse_errors += 1; parse_errors += 1;
return;
} }
} }