Logic gates can take part select inputs
It is possible for the compiler to generate logic gates that have inputs from part select nodes. This implements the part select input methods. Signed-off-by: Stephen Williams <steve@icarus.com>
This commit is contained in:
Stephen Williams
parent
86e6817505
commit
11ec505697
113
vvp/logic.cc
113
vvp/logic.cc
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2001-2004 Stephen Williams (steve@icarus.com)
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* Copyright (c) 2001-2007 Stephen Williams (steve@icarus.com)
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*
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*
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* This source code is free software; you can redistribute it
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* and/or modify it in source code form under the terms of the GNU
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@ -104,6 +104,24 @@ void vvp_fun_boolean_::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit)
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}
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}
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}
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}
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void vvp_fun_boolean_::recv_vec4_pv(vvp_net_ptr_t ptr, const vvp_vector4_t&bit,
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unsigned base, unsigned wid, unsigned vwid)
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{
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unsigned port = ptr.port();
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assert(bit.size() == wid);
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assert(base + bit.size() <= vwid);
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if (input_[port].subvalue(base, wid) .eeq( bit ))
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return;
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input_[port] .set_vec(base, bit);
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if (net_ == 0) {
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net_ = ptr.ptr();
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schedule_generic(this, 0, false);
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}
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}
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vvp_fun_and::vvp_fun_and(unsigned wid, bool invert)
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vvp_fun_and::vvp_fun_and(unsigned wid, bool invert)
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: vvp_fun_boolean_(wid), invert_(invert)
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: vvp_fun_boolean_(wid), invert_(invert)
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{
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{
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@ -616,96 +634,3 @@ void compile_functor(char*label, char*type, unsigned width,
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define_functor_symbol(label, net_drv);
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define_functor_symbol(label, net_drv);
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free(label);
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free(label);
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}
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}
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/*
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* $Log: logic.cc,v $
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* Revision 1.38 2007/02/12 05:08:27 steve
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* NAND output is inverted once AFTER AND is calculated.
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*
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* Revision 1.37 2006/11/28 05:57:20 steve
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* Use new vvp_fun_XXX in place of old functor table for NAND/NOR/XNOR/EEQ.
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*
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* Revision 1.36 2006/01/02 05:32:07 steve
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* Require explicit delay node from source.
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*
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* Revision 1.35 2005/09/19 22:47:28 steve
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* Prevent some excess scheduling of logic propagation events.
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*
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* Revision 1.34 2005/09/19 21:45:09 steve
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* Use lazy eval of BUF/NOT/OR/XOR gates.
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*
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* Revision 1.33 2005/09/01 04:08:47 steve
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* Support MUXR functors.
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*
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* Revision 1.32 2005/07/06 04:29:25 steve
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* Implement real valued signals and arith nodes.
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*
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* Revision 1.31 2005/06/26 21:08:38 steve
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* AND functor explicitly knows its width.
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*
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* Revision 1.30 2005/06/26 18:06:29 steve
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* AND gates propogate through scheduler, not directly.
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*
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* Revision 1.29 2005/06/22 00:04:49 steve
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* Reduce vvp_vector4 copies by using const references.
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*
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* Revision 1.28 2005/06/21 22:48:23 steve
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* Optimize vvp_scalar_t handling, and fun_buf Z handling.
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*
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* Revision 1.27 2005/06/17 03:46:52 steve
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* Make functors know their own width.
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*
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* Revision 1.26 2005/06/12 15:13:37 steve
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* Support resistive mos devices.
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*
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* Revision 1.25 2005/06/12 00:44:49 steve
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* Implement nmos and pmos devices.
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*
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* Revision 1.24 2005/06/02 16:02:11 steve
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* Add support for notif0/1 gates.
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* Make delay nodes support inertial delay.
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* Add the %force/link instruction.
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*
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* Revision 1.23 2005/05/14 19:43:23 steve
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* Move functor delays to vvp_delay_fun object.
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*
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* Revision 1.22 2005/05/13 05:13:12 steve
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* Give buffers support for simple delays.
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*
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* Revision 1.21 2005/04/13 06:34:20 steve
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* Add vvp driver functor for logic outputs,
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* Add ostream output operators for debugging.
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*
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* Revision 1.20 2005/04/03 05:45:51 steve
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* Rework the vvp_delay_t class.
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*
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* Revision 1.19 2005/02/12 22:50:52 steve
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* Implement the vvp_fun_muxz functor.
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*
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* Revision 1.18 2005/02/07 22:42:42 steve
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* Add .repeat functor and BIFIF functors.
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*
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* Revision 1.17 2005/01/29 17:52:06 steve
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* move AND to buitin instead of table.
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*
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* Revision 1.16 2004/12/31 05:56:36 steve
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* Add specific BUFZ functor.
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*
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* Revision 1.15 2004/12/29 23:45:13 steve
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* Add the part concatenation node (.concat).
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*
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* Add a vvp_event_anyedge class to handle the special
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* case of .event statements of edge type. This also
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* frees the posedge/negedge types to handle all 4 inputs.
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*
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* Implement table functor recv_vec4 method to receive
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* and process vectors.
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*
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* Revision 1.14 2004/12/11 02:31:29 steve
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* Rework of internals to carry vectors through nexus instead
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* of single bits. Make the ivl, tgt-vvp and vvp initial changes
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* down this path.
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*
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*/
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69
vvp/logic.h
69
vvp/logic.h
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@ -1,7 +1,7 @@
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#ifndef __logic_H
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#ifndef __logic_H
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#define __logic_H
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#define __logic_H
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/*
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/*
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* Copyright (c) 2000-2005 Stephen Williams (steve@icarus.com)
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* Copyright (c) 2000-2007 Stephen Williams (steve@icarus.com)
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*
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*
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* This source code is free software; you can redistribute it
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* and/or modify it in source code form under the terms of the GNU
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@ -54,7 +54,10 @@ class vvp_fun_boolean_ : public vvp_net_fun_t, protected vvp_gen_event_s {
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public:
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public:
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explicit vvp_fun_boolean_(unsigned wid);
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explicit vvp_fun_boolean_(unsigned wid);
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~vvp_fun_boolean_();
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~vvp_fun_boolean_();
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void recv_vec4(vvp_net_ptr_t p, const vvp_vector4_t&bit);
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void recv_vec4(vvp_net_ptr_t p, const vvp_vector4_t&bit);
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void recv_vec4_pv(vvp_net_ptr_t p, const vvp_vector4_t&bit,
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unsigned base, unsigned wid, unsigned vwid);
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protected:
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protected:
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vvp_vector4_t input_[4];
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vvp_vector4_t input_[4];
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@ -206,68 +209,4 @@ extern const unsigned char ft_EEQ[];
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extern const unsigned char ft_TRIAND[];
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extern const unsigned char ft_TRIAND[];
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extern const unsigned char ft_TRIOR[];
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extern const unsigned char ft_TRIOR[];
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/*
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* $Log: logic.h,v $
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* Revision 1.25 2006/11/28 05:57:20 steve
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* Use new vvp_fun_XXX in place of old functor table for NAND/NOR/XNOR/EEQ.
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*
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* Revision 1.24 2005/09/19 21:45:09 steve
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* Use lazy eval of BUF/NOT/OR/XOR gates.
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*
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* Revision 1.23 2005/09/01 04:08:47 steve
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* Support MUXR functors.
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*
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* Revision 1.22 2005/07/06 04:29:25 steve
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* Implement real valued signals and arith nodes.
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*
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* Revision 1.21 2005/06/26 21:08:38 steve
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* AND functor explicitly knows its width.
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*
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* Revision 1.20 2005/06/26 18:06:30 steve
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* AND gates propogate through scheduler, not directly.
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*
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* Revision 1.19 2005/06/22 00:04:49 steve
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* Reduce vvp_vector4 copies by using const references.
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*
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* Revision 1.18 2005/06/17 03:46:53 steve
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* Make functors know their own width.
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*
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* Revision 1.17 2005/06/12 21:56:16 steve
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* Remove unused ft_MOS truth tables.
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*
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* Revision 1.16 2005/05/14 19:43:23 steve
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* Move functor delays to vvp_delay_fun object.
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*
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* Revision 1.15 2005/05/13 05:13:12 steve
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* Give buffers support for simple delays.
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*
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* Revision 1.14 2005/04/13 06:34:20 steve
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* Add vvp driver functor for logic outputs,
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* Add ostream output operators for debugging.
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*
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* Revision 1.13 2005/02/12 23:05:25 steve
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* Cleanup unused truth tables.
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*
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* Revision 1.11 2005/01/29 17:52:06 steve
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* move AND to buitin instead of table.
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*
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* Revision 1.10 2004/12/31 05:56:36 steve
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* Add specific BUFZ functor.
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*
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* Revision 1.9 2004/12/29 23:45:13 steve
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* Add the part concatenation node (.concat).
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*
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* Add a vvp_event_anyedge class to handle the special
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* case of .event statements of edge type. This also
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* frees the posedge/negedge types to handle all 4 inputs.
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*
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* Implement table functor recv_vec4 method to receive
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* and process vectors.
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*
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* Revision 1.8 2004/12/11 02:31:29 steve
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* Rework of internals to carry vectors through nexus instead
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* of single bits. Make the ivl, tgt-vvp and vvp initial changes
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* down this path.
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*
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*/
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#endif // __logic_H
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#endif // __logic_H
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