Replace type classes with enumeration
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79558910d1
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110a1b2ac7
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@ -42,7 +42,7 @@ static vhdl_expr *translate_signal(ivl_expr_t e)
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ivl_signal_t sig = ivl_expr_signal(e);
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// Assume all signals are single bits at the moment
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vhdl_type *type = vhdl_scalar_type::std_logic();
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vhdl_type *type = vhdl_type::std_logic();
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return new vhdl_var_ref(ivl_signal_basename(sig), type);
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}
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@ -37,9 +37,9 @@ static void declare_signals(vhdl_arch *arch, ivl_scope_t scope)
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int width = ivl_signal_width(sig);
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vhdl_type *sig_type;
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if (width > 0)
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sig_type = vhdl_scalar_type::std_logic();
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sig_type = vhdl_type::std_logic();
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else
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sig_type = vhdl_vector_type::std_logic_vector(width-1, 0);
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sig_type = vhdl_type::std_logic_vector(width-1, 0);
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vhdl_signal_decl *decl =
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new vhdl_signal_decl(ivl_signal_basename(sig), sig_type);
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arch->add_decl(decl);
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@ -45,9 +45,8 @@ static int draw_stask_display(vhdl_process *proc, ivl_statement_t stmt)
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const char *display_line = "Verilog_Display_Line";
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if (!proc->have_declared_var(display_line)) {
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vhdl_type *line_type = new vhdl_scalar_type("Line");
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vhdl_var_decl *line_var =
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new vhdl_var_decl(display_line, line_type);
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new vhdl_var_decl(display_line, vhdl_type::line());
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line_var->set_comment("For generating $display output");
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proc->add_decl(line_var);
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}
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@ -67,12 +66,12 @@ static int draw_stask_display(vhdl_process *proc, ivl_statement_t stmt)
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// Need to add a call to Type'Image for types not
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// supported by std.textio
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if (base->get_type()->get_name() != "String") {
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std::string name(base->get_type()->get_name());
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if (base->get_type()->get_name() != VHDL_TYPE_STRING) {
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std::string name(base->get_type()->get_string());
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name += "'Image";
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vhdl_fcall *cast
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= new vhdl_fcall(name.c_str(), vhdl_scalar_type::string());
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= new vhdl_fcall(name.c_str(), vhdl_type::string());
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cast->add_expr(base);
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e = cast;
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}
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@ -84,7 +83,7 @@ static int draw_stask_display(vhdl_process *proc, ivl_statement_t stmt)
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vhdl_pcall_stmt *write = new vhdl_pcall_stmt("Write");
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vhdl_var_ref *ref =
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new vhdl_var_ref(display_line, vhdl_scalar_type::line());
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new vhdl_var_ref(display_line, vhdl_type::line());
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write->add_expr(ref);
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write->add_expr(e);
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@ -94,10 +93,10 @@ static int draw_stask_display(vhdl_process *proc, ivl_statement_t stmt)
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// WriteLine(Output, Verilog_Display_Line)
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vhdl_pcall_stmt *write_line = new vhdl_pcall_stmt("WriteLine");
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vhdl_var_ref *output_ref =
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new vhdl_var_ref("std.textio.Output", new vhdl_scalar_type("File"));
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new vhdl_var_ref("std.textio.Output", new vhdl_type(VHDL_TYPE_FILE));
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write_line->add_expr(output_ref);
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vhdl_var_ref *ref =
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new vhdl_var_ref(display_line, vhdl_scalar_type::line());
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new vhdl_var_ref(display_line, vhdl_type::line());
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write_line->add_expr(ref);
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proc->add_stmt(write_line);
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@ -170,7 +169,7 @@ static int draw_nbassign(vhdl_process *proc, ivl_statement_t stmt)
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vhdl_expr *rhs_raw = translate_expr(ivl_stmt_rval(stmt));
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if (NULL == rhs_raw)
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return 1;
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vhdl_expr *rhs = decl->get_type()->cast(rhs_raw);
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vhdl_expr *rhs = rhs_raw->cast(decl->get_type());
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// The type here can be null as it is never actually needed
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vhdl_var_ref *lval_ref = new vhdl_var_ref(signame, NULL);
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@ -25,6 +25,7 @@
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#include <cstring>
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#include <typeinfo>
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#include <iostream>
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#include <sstream>
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static const int VHDL_INDENT = 2; // Spaces to indent
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@ -344,31 +345,67 @@ void vhdl_wait_stmt::emit(std::ofstream &of, int level) const
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of << "wait;";
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}
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vhdl_scalar_type *vhdl_scalar_type::std_logic()
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vhdl_type *vhdl_type::std_logic()
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{
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return new vhdl_scalar_type("std_logic");
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return new vhdl_type(VHDL_TYPE_STD_LOGIC);
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}
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vhdl_scalar_type *vhdl_scalar_type::string()
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vhdl_type *vhdl_type::string()
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{
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return new vhdl_scalar_type("String");
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return new vhdl_type(VHDL_TYPE_STRING);
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}
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vhdl_scalar_type *vhdl_scalar_type::line()
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vhdl_type *vhdl_type::line()
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{
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return new vhdl_scalar_type("Line");
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return new vhdl_type(VHDL_TYPE_LINE);
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}
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void vhdl_scalar_type::emit(std::ofstream &of, int level) const
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std::string vhdl_type::get_string() const
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{
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of << name_;
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switch (name_) {
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case VHDL_TYPE_STD_LOGIC:
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return std::string("std_logic");
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case VHDL_TYPE_STD_LOGIC_VECTOR:
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{
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std::ostringstream ss;
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ss << "std_logic_vector(" << msb_;
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ss << " downto " << lsb_ << ")";
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return ss.str();
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}
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case VHDL_TYPE_STRING:
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return std::string("String");
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case VHDL_TYPE_LINE:
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return std::string("Line");
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case VHDL_TYPE_FILE:
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return std::string("File");
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default:
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return std::string("BadType");
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}
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}
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void vhdl_type::emit(std::ofstream &of, int level) const
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{
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of << get_string();
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}
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/*
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* The default cast just assumes there's a VHDL cast function to
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* do the job for us.
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*/
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vhdl_expr *vhdl_expr::cast(const vhdl_type *to)
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{
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vhdl_fcall *conv =
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new vhdl_fcall(to->get_string().c_str(), new vhdl_type(*to));
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conv->add_expr(this);
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return conv;
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}
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/*
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* Cast something to a scalar type. There are a few ugly hacks here
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* to handle special cases.
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*/
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vhdl_expr *vhdl_scalar_type::cast(vhdl_expr *expr) const
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/*vhdl_expr *vhdl_scalar_type::cast(vhdl_expr *expr) const
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{
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if (typeid(*expr) == typeid(vhdl_const_bits)
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&& name_ == "std_logic") {
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@ -396,21 +433,11 @@ vhdl_expr *vhdl_scalar_type::cast(vhdl_expr *expr) const
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return conv;
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}
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}
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}*/
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vhdl_vector_type *vhdl_vector_type::std_logic_vector(int msb, int lsb)
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vhdl_type *vhdl_type::std_logic_vector(int msb, int lsb)
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{
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return new vhdl_vector_type("std_logic_vector", msb, lsb);
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}
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void vhdl_vector_type::emit(std::ofstream &of, int level) const
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{
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of << name_ << "(" << msb_ << " downto " << lsb_ << ")";
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}
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vhdl_expr *vhdl_vector_type::cast(vhdl_expr *expr) const
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{
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return expr;
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return new vhdl_type(VHDL_TYPE_STD_LOGIC_VECTOR, msb, lsb);
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}
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vhdl_var_decl::~vhdl_var_decl()
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@ -510,7 +537,7 @@ void vhdl_nbassign_stmt::emit(std::ofstream &of, int level) const
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}
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vhdl_const_bits::vhdl_const_bits(const char *value)
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: vhdl_expr(vhdl_vector_type::std_logic_vector(strlen(value)-1, 0)),
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: vhdl_expr(vhdl_type::std_logic_vector(strlen(value)-1, 0)),
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value_(value)
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{
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@ -50,16 +50,13 @@ private:
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typedef std::list<vhdl_element*> element_list_t;
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class vhdl_type : public vhdl_element {
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public:
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vhdl_type(const char *name) : name_(name) {}
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virtual ~vhdl_type() {}
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virtual vhdl_expr *cast(vhdl_expr *expr) const = 0;
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const std::string &get_name() const { return name_; }
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protected:
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std::string name_;
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enum vhdl_type_name_t {
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VHDL_TYPE_STD_LOGIC,
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VHDL_TYPE_STD_LOGIC_VECTOR,
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VHDL_TYPE_STRING,
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VHDL_TYPE_LINE,
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VHDL_TYPE_FILE
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};
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/*
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@ -67,43 +64,35 @@ protected:
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* too much more complex, as Verilog's type system is much
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* simpler than VHDL's.
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*/
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class vhdl_scalar_type : public vhdl_type {
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class vhdl_type : public vhdl_element {
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public:
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vhdl_scalar_type(const char *name)
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: vhdl_type(name) {}
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vhdl_type(vhdl_type_name_t name, int msb = 0, int lsb = 0)
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: name_(name), msb_(msb), lsb_(lsb) {}
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virtual ~vhdl_type() {}
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void emit(std::ofstream &of, int level) const;
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vhdl_expr *cast(vhdl_expr *expr) const;
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vhdl_type_name_t get_name() const { return name_; }
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std::string get_string() const;
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int get_width() const { return msb_ - lsb_ + 1; }
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// Common types
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static vhdl_scalar_type *std_logic();
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static vhdl_scalar_type *string();
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static vhdl_scalar_type *line();
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};
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/*
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* A vector type like std_logic_vector.
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*/
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class vhdl_vector_type : public vhdl_type {
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public:
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vhdl_vector_type(const char *name, int msb, int lsb)
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: vhdl_type(name), msb_(msb), lsb_(lsb) {}
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void emit(std::ofstream &of, int level) const;
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vhdl_expr *cast(vhdl_expr *expr) const;
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// Common types
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static vhdl_vector_type *std_logic_vector(int msb, int lsb);
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private:
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static vhdl_type *std_logic();
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static vhdl_type *string();
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static vhdl_type *line();
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static vhdl_type *std_logic_vector(int msb, int lsb);
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protected:
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vhdl_type_name_t name_;
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int msb_, lsb_;
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};
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class vhdl_expr : public vhdl_element {
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public:
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vhdl_expr(vhdl_type* type) : type_(type) {}
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virtual ~vhdl_expr();
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const vhdl_type *get_type() const { return type_; }
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virtual vhdl_expr *cast(const vhdl_type *to);
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private:
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vhdl_type *type_;
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};
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@ -126,7 +115,7 @@ private:
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class vhdl_const_string : public vhdl_expr {
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public:
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vhdl_const_string(const char *value)
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: vhdl_expr(vhdl_scalar_type::string()), value_(value) {}
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: vhdl_expr(vhdl_type::string()), value_(value) {}
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void emit(std::ofstream &of, int level) const;
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private:
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@ -145,7 +134,7 @@ private:
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class vhdl_const_bit : public vhdl_expr {
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public:
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vhdl_const_bit(char bit)
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: vhdl_expr(vhdl_scalar_type::std_logic()), bit_(bit) {}
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: vhdl_expr(vhdl_type::std_logic()), bit_(bit) {}
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void emit(std::ofstream &of, int level) const;
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private:
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char bit_;
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