Fully elaborate Sequential UDP behavior.
This commit is contained in:
steve
parent
45f45f73b7
commit
10b345bd16
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: design_dump.cc,v 1.7 1998/12/07 04:53:17 steve Exp $"
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#ident "$Id: design_dump.cc,v 1.8 1998/12/14 02:01:34 steve Exp $"
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#endif
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/*
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@ -167,9 +167,55 @@ void NetLogic::dump_node(ostream&o, unsigned ind) const
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dump_obj_attr(o, ind+4);
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}
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void NetUDP::dump_node(ostream&o, unsigned ind) const
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void NetUDP::dump_sequ_(ostream&o, unsigned ind) const
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{
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o << setw(ind) << "" << "UDP: ";
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string tmp = "";
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for (unsigned idx = 0 ; idx < ind ; idx += 1)
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tmp += " ";
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o << tmp << "Sequential UDP" << " #(" << delay1() <<
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"," << delay2() << "," << delay3() << ") " << name() <<
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endl;
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for (FSM_::const_iterator ent = fsm_.begin()
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; ent != fsm_.end() ; ent++) {
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o << setw(ind+6) << "" << (*ent).first << " -->";
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state_t_*st = (*ent).second;
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assert((*ent).first[0] == st->out);
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for (unsigned idx = 1 ; idx < pin_count() ; idx += 1) {
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string tmp = (*ent).first;
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if (st->pins[idx].zer) {
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tmp[0] = st->pins[idx].zer->out;
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tmp[idx] = '0';
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o << " " << tmp;
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}
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if (st->pins[idx].one) {
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tmp[0] = st->pins[idx].one->out;
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tmp[idx] = '1';
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o << " " << tmp;
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}
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if (st->pins[idx].xxx) {
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tmp[0] = st->pins[idx].xxx->out;
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tmp[idx] = 'x';
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o << " " << tmp;
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}
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}
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o << endl;
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}
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o << setw(ind+6) << "" << "initial value == " << init_ << endl;
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dump_node_pins(o, ind+4);
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dump_obj_attr(o, ind+4);
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}
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void NetUDP::dump_comb_(ostream&o, unsigned ind) const
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{
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o << setw(ind) << "" << "Combinational UDP: ";
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o << " #(" << delay1() << "," << delay2() << "," << delay3() <<
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") " << name() << endl;
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@ -177,6 +223,14 @@ void NetUDP::dump_node(ostream&o, unsigned ind) const
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dump_obj_attr(o, ind+4);
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}
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void NetUDP::dump_node(ostream&o, unsigned ind) const
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{
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if (sequential_)
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dump_sequ_(o, ind);
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else
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dump_comb_(o, ind);
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}
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void NetPEvent::dump_node(ostream&o, unsigned ind) const
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{
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o << setw(ind) << "" << "event: ";
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@ -407,6 +461,9 @@ void Design::dump(ostream&o) const
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/*
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* $Log: design_dump.cc,v $
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* Revision 1.8 1998/12/14 02:01:34 steve
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* Fully elaborate Sequential UDP behavior.
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*
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* Revision 1.7 1998/12/07 04:53:17 steve
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* Generate OBUF or IBUF attributes (and the gates
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* to garry them) where a wire is a pad. This involved
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42
elaborate.cc
42
elaborate.cc
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: elaborate.cc,v 1.9 1998/12/07 04:53:17 steve Exp $"
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#ident "$Id: elaborate.cc,v 1.10 1998/12/14 02:01:34 steve Exp $"
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#endif
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/*
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@ -255,12 +255,20 @@ void PGModule::elaborate_mod_(Design*des, Module*rmod, const string&path) const
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}
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}
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/*
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* From a UDP definition in the source, make a NetUDP
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* object. Elaborate the pin expressions as netlists, then connect
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* those networks to the pins.
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*/
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void PGModule::elaborate_udp_(Design*des, PUdp*udp, const string&path) const
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{
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const string my_name = path+"."+get_name();
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NetUDP*net = new NetUDP(my_name, udp->ports.size());
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NetUDP*net = new NetUDP(my_name, udp->ports.size(), udp->sequential);
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net->set_attributes(udp->attributes);
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/* Run through the pins, making netlists for the pin
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expressions and connecting them to the pin in question. All
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of this is independent of the nature of the UDP. */
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for (unsigned idx = 0 ; idx < net->pin_count() ; idx += 1) {
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if (pin(idx) == 0)
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continue;
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@ -274,10 +282,37 @@ void PGModule::elaborate_udp_(Design*des, PUdp*udp, const string&path) const
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connect(sig->pin(0), net->pin(idx));
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// Delete excess holding signal.
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if (NetTmp*tmp = dynamic_cast<NetTmp*>(sig))
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delete tmp;
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}
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/* Build up the truth table for the netlist from the input
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strings. */
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for (unsigned idx = 0 ; idx < udp->tinput.size() ; idx += 1) {
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string input = udp->sequential
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? (string("") + udp->tcurrent[idx] + udp->tinput[idx])
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: udp->tinput[idx];
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net->set_table(input, udp->toutput[idx]);
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}
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net->cleanup_table();
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if (udp->sequential) switch (udp->initial) {
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case verinum::V0:
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net->set_initial('0');
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break;
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case verinum::V1:
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net->set_initial('1');
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break;
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case verinum::Vx:
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case verinum::Vz:
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net->set_initial('x');
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break;
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}
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// All done. Add the object to the design.
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des->add_node(net);
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}
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@ -734,6 +769,9 @@ Design* elaborate(const map<string,Module*>&modules,
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/*
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* $Log: elaborate.cc,v $
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* Revision 1.10 1998/12/14 02:01:34 steve
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* Fully elaborate Sequential UDP behavior.
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*
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* Revision 1.9 1998/12/07 04:53:17 steve
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* Generate OBUF or IBUF attributes (and the gates
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* to garry them) where a wire is a pad. This involved
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210
netlist.cc
210
netlist.cc
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: netlist.cc,v 1.11 1998/12/07 04:53:17 steve Exp $"
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#ident "$Id: netlist.cc,v 1.12 1998/12/14 02:01:35 steve Exp $"
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#endif
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# include <cassert>
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@ -423,12 +423,213 @@ NetLogic::NetLogic(const string&n, unsigned pins, TYPE t)
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pin(idx).set_dir(Link::INPUT);
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}
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NetUDP::NetUDP(const string&n, unsigned pins)
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: NetNode(n, pins)
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NetUDP::NetUDP(const string&n, unsigned pins, bool sequ)
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: NetNode(n, pins), sequential_(sequ), init_('x')
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{
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pin(0).set_dir(Link::OUTPUT);
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for (unsigned idx = 1 ; idx < pins ; idx += 1)
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pin(idx).set_dir(Link::INPUT);
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}
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NetUDP::state_t_* NetUDP::find_state_(const string&str)
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{
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map<string,state_t_*>::iterator cur = fsm_.find(str);
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if (cur != fsm_.end())
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return (*cur).second;
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state_t_*st = fsm_[str];
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if (st == 0) {
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st = new state_t_(pin_count());
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st->out = str[0];
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fsm_[str] = st;
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}
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return st;
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}
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/*
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* This method takes the input string, which contains exactly one
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* edge, and connects it to the correct output state. The output state
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* will be generated if needed, and the value compared.
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*/
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bool NetUDP::set_sequ_(const string&input, char output)
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{
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if (output == '-')
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output = input[0];
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string frm = input;
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string to = input;
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to[0] = output;
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unsigned edge = frm.find_first_not_of("01x");
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assert(frm.find_last_not_of("01x") == edge);
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switch (input[edge]) {
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case 'r':
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frm[edge] = '0';
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to[edge] = '1';
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break;
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case 'R':
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frm[edge] = 'x';
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to[edge] = '1';
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break;
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case 'f':
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frm[edge] = '1';
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to[edge] = '0';
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break;
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case 'F':
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frm[edge] = 'x';
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to[edge] = '0';
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break;
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case 'P':
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frm[edge] = '0';
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to[edge] = 'x';
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break;
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case 'N':
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frm[edge] = '1';
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to[edge] = 'x';
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break;
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default:
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assert(0);
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}
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state_t_*sfrm = find_state_(frm);
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state_t_*sto = find_state_(to);
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switch (to[edge]) {
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case '0':
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assert(sfrm->pins[edge].zer == 0);
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sfrm->pins[edge].zer = sto;
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break;
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case '1':
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assert(sfrm->pins[edge].one == 0);
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sfrm->pins[edge].one = sto;
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break;
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case 'x':
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assert(sfrm->pins[edge].xxx == 0);
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sfrm->pins[edge].xxx = sto;
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break;
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}
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return true;
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}
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bool NetUDP::sequ_glob_(string input, char output)
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{
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for (unsigned idx = 0 ; idx < input.length() ; idx += 1)
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switch (input[idx]) {
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case '0':
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case '1':
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case 'x':
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case 'r':
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case 'R':
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case 'f':
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case 'F':
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case 'P':
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case 'N':
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break;
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case '?': // Iterate over all the levels
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input[idx] = '0';
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sequ_glob_(input, output);
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input[idx] = '1';
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sequ_glob_(input, output);
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input[idx] = 'x';
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sequ_glob_(input, output);
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return true;
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case '*': // Iterate over all the edges
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input[idx] = 'r';
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sequ_glob_(input, output);
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input[idx] = 'R';
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sequ_glob_(input, output);
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input[idx] = 'f';
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sequ_glob_(input, output);
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input[idx] = 'F';
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sequ_glob_(input, output);
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input[idx] = 'P';
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sequ_glob_(input, output);
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input[idx] = 'N';
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sequ_glob_(input, output);
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return true;
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default:
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assert(0);
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}
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return set_sequ_(input, output);
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}
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bool NetUDP::set_table(const string&input, char output)
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{
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assert((output == '0') || (output == '1') || (sequential_ &&
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(output == '-')));
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if (sequential_) {
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assert(input.length() == pin_count());
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/* XXXX Need to check to make sure that the input vector
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contains a legal combination of characters. */
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return sequ_glob_(input, output);
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} else {
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assert(input.length() == (pin_count()-1));
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/* XXXX Need to check to make sure that the input vector
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contains a legal combination of characters. In
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combinational UDPs, only 0, 1 and x are allowed. */
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assert(0);
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return true;
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}
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}
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void NetUDP::cleanup_table()
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{
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for (FSM_::iterator idx = fsm_.begin() ; idx != fsm_.end() ; idx++) {
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string str = (*idx).first;
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state_t_*st = (*idx).second;
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assert(str[0] == st->out);
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for (unsigned pin = 0 ; pin < pin_count() ; pin += 1) {
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if (st->pins[pin].zer && st->pins[pin].zer->out == 'x')
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st->pins[pin].zer = 0;
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if (st->pins[pin].one && st->pins[pin].one->out == 'x')
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st->pins[pin].one = 0;
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if (st->pins[pin].xxx && st->pins[pin].xxx->out == 'x')
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st->pins[pin].xxx = 0;
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}
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}
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for (FSM_::iterator idx = fsm_.begin() ; idx != fsm_.end() ; ) {
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FSM_::iterator cur = idx;
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idx ++;
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state_t_*st = (*cur).second;
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if (st->out != 'x')
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continue;
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for (unsigned pin = 0 ; pin < pin_count() ; pin += 1) {
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if (st->pins[pin].zer)
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goto break_label;
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if (st->pins[pin].one)
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goto break_label;
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if (st->pins[pin].xxx)
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goto break_label;
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}
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//delete st;
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fsm_.erase(cur);
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break_label:;
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}
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}
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void NetUDP::set_initial(char val)
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{
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assert(sequential_);
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assert((val == '0') || (val == '1') || (val == 'x'));
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init_ = val;
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}
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string Design::get_flag(const string&key) const
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@ -583,6 +784,9 @@ NetNet* Design::find_signal(bool (*func)(const NetNet*))
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/*
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* $Log: netlist.cc,v $
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* Revision 1.12 1998/12/14 02:01:35 steve
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* Fully elaborate Sequential UDP behavior.
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*
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* Revision 1.11 1998/12/07 04:53:17 steve
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* Generate OBUF or IBUF attributes (and the gates
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* to garry them) where a wire is a pad. This involved
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|
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84
netlist.h
84
netlist.h
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@ -19,7 +19,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
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*/
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#if !defined(WINNT)
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#ident "$Id: netlist.h,v 1.11 1998/12/07 04:53:17 steve Exp $"
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#ident "$Id: netlist.h,v 1.12 1998/12/14 02:01:35 steve Exp $"
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#endif
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/*
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@ -338,14 +338,91 @@ class NetLogic : public NetNode {
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* The UDP is a User Defined Primitive from the Verilog source. Do not
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* expand it out any further then this in the netlist, as this can be
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* used to represent target device primitives.
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*
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* The UDP can be combinational or sequential. The sequentianl UDP
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* includes the current output in the truth table, and supports edges,
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* whereas the combinational does not and is entirely level sensitive.
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* In any case, pin 0 is an output, and all the remaining pins are
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* inputs.
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*
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* The truth table is canonically represented as a finite state
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* machine with the current state representing the inputs and the
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* current output, and the next state carrying the new output value to
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* use. All the outgoing transitions from a state represent a single
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* edge.
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*
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* Set_table takes as input a string with one letter per pin. The
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* valid characters are:
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*
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* 0, 1, x -- The levels
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* r -- (01)
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* R -- (x1)
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* f -- (10)
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* F -- (x0)
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* P -- (0x)
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* N -- (1x)
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*
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* COMBINATIONAL
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* The logic table is a map between the input levels and the
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* output. Each input pin can have the value 0, 1 or x and the output
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* can have the values 0 or 1. If the input matches nothing, the
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* output is x. In canonical form, only the entries that generate 0 or
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* 1 are listed.
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*
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* SEQUENTIAL
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* These objects have a single bit of memory. The logic table includes
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* an entry for the current value, and allows edges on the inputs. In
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* canonical form, inly then entries that generate 0, 1 or - (no change)
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* are listed.
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*
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*/
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class NetUDP : public NetNode {
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public:
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explicit NetUDP(const string&n, unsigned pins);
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explicit NetUDP(const string&n, unsigned pins, bool sequ =false);
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virtual void emit_node(ostream&, struct target_t*) const;
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virtual void dump_node(ostream&, unsigned ind) const;
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/* return false if the entry conflicts with an existing
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entry. In any case, the new output overrides. */
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bool set_table(const string&input, char output);
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void cleanup_table();
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||||
void set_initial(char);
|
||||
|
||||
bool is_sequential() const { return sequential_; }
|
||||
|
||||
private:
|
||||
const bool sequential_;
|
||||
char init_;
|
||||
|
||||
struct state_t_;
|
||||
struct pin_t_ {
|
||||
state_t_*zer;
|
||||
state_t_*one;
|
||||
state_t_*xxx;
|
||||
|
||||
explicit pin_t_() : zer(0), one(0), xxx(0) { }
|
||||
};
|
||||
|
||||
struct state_t_ {
|
||||
char out;
|
||||
pin_t_*pins;
|
||||
|
||||
state_t_(unsigned n) : out(0), pins(new pin_t_[n]) {}
|
||||
~state_t_() { delete[]pins; }
|
||||
};
|
||||
|
||||
typedef map<string,state_t_*> FSM_;
|
||||
FSM_ fsm_;
|
||||
bool set_sequ_(const string&in, char out);
|
||||
bool sequ_glob_(string, char out);
|
||||
|
||||
state_t_*find_state_(const string&);
|
||||
|
||||
void dump_sequ_(ostream&o, unsigned ind) const;
|
||||
void dump_comb_(ostream&o, unsigned ind) const;
|
||||
};
|
||||
|
||||
/* =========
|
||||
|
|
@ -811,6 +888,9 @@ extern ostream& operator << (ostream&, NetNet::Type);
|
|||
|
||||
/*
|
||||
* $Log: netlist.h,v $
|
||||
* Revision 1.12 1998/12/14 02:01:35 steve
|
||||
* Fully elaborate Sequential UDP behavior.
|
||||
*
|
||||
* Revision 1.11 1998/12/07 04:53:17 steve
|
||||
* Generate OBUF or IBUF attributes (and the gates
|
||||
* to garry them) where a wire is a pad. This involved
|
||||
|
|
|
|||
4
parse.y
4
parse.y
|
|
@ -19,7 +19,7 @@
|
|||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
#if !defined(WINNT)
|
||||
#ident "$Id: parse.y,v 1.8 1998/12/01 00:42:14 steve Exp $"
|
||||
#ident "$Id: parse.y,v 1.9 1998/12/14 02:01:35 steve Exp $"
|
||||
#endif
|
||||
|
||||
# include "parse_misc.h"
|
||||
|
|
@ -730,7 +730,7 @@ udp_input_sym
|
|||
| 'b' { $$ = 'b'; }
|
||||
| '*' { $$ = '*'; }
|
||||
| 'f' { $$ = 'f'; }
|
||||
| 'r' { $$ = 'f'; }
|
||||
| 'r' { $$ = 'r'; }
|
||||
;
|
||||
|
||||
udp_output_sym
|
||||
|
|
|
|||
Loading…
Reference in New Issue