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parse.y: Mark enum output ports always as IMPLICT_REG 

Unless explicitly declared a wire an enum output port is of variable type
and should be marked as IMPLICT_REG.

Currently this is only done when the base type of the enum is `logic`. But
it should be done for all enums regardless of their base type.

Without this change for example the following snippet

```
  typedef enum {
      A,
      B
  } E;

  module M (
      input E ei,
      output E eo
  );

      always_comb eo = ei;

  endmodule
```

fails with the following error message

  test_enum.sv:11: error: eo is not a valid l-value in M.
  test_enum.sv:8:       : eo is declared here as wire.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
This commit is contained in:
Lars-Peter Clausen 2020-09-20 18:59:10 +02:00
parent b8c5fd6314
commit 1064543d27
1 changed files with 2 additions and 3 deletions
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5
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@ -4659,9 +4659,8 @@ port_declaration
use_type = NetNet::IMPLICIT_REG;
} else if (dynamic_cast<struct_type_t*> ($4)) {
use_type = NetNet::IMPLICIT_REG;
} else if (enum_type_t*etype = dynamic_cast<enum_type_t*> ($4)) {
if(etype->base_type == IVL_VT_LOGIC)
use_type = NetNet::IMPLICIT_REG;
} else if (dynamic_cast<enum_type_t*> ($4)) {
use_type = NetNet::IMPLICIT_REG;
}
}
ptmp = pform_module_port_reference(name, @2.text, @2.first_line);