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Prepare for 0.8.6 release.

This commit is contained in:
Stephen Williams 2007-11-26 10:55:13 -08:00
parent a44236f8cb
commit 0f716d6dca
2 changed files with 4 additions and 4 deletions
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2
Makefile.in
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@ -25,7 +25,7 @@ SHELL = /bin/sh
# by the compiler. It reflects the assigned version number for the # by the compiler. It reflects the assigned version number for the
# product as a whole. Most components also print the CVS Name: token # product as a whole. Most components also print the CVS Name: token
# in order to get a more automatic version stamp as well. # in order to get a more automatic version stamp as well.
VERSION = 0.8.4 VERSION = 0.8.6
prefix = @prefix@ prefix = @prefix@
exec_prefix = @exec_prefix@ exec_prefix = @exec_prefix@

6
verilog.spec
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@ -1,10 +1,10 @@
Summary: Icarus Verilog Summary: Icarus Verilog
Name: verilog Name: verilog
Version: 0.8.4 Version: 0.8.6
Release: 0 Release: 0
License: GPL License: GPL
Group: Applications/Engineering Group: Applications/Engineering
Source: ftp://icarus.com/pub/eda/verilog/v0.8/verilog-0.8.4.tar.gz Source: ftp://icarus.com/pub/eda/verilog/v0.8/verilog-0.8.6.tar.gz
URL: http://www.icarus.com/eda/verilog/index.html URL: http://www.icarus.com/eda/verilog/index.html
Packager: Stephen Williams <steve@icarus.com> Packager: Stephen Williams <steve@icarus.com>
@ -29,7 +29,7 @@ engineering formats, including simulation. It strives to be true
to the IEEE-1364 standard. to the IEEE-1364 standard.
%prep %prep
%setup -n verilog-0.8.4 %setup -n verilog-0.8.6
%build %build
%ifarch x86_64 %ifarch x86_64