luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Correct misleading comment

This commit is contained in:
Nick Gasson 2008-06-13 14:47:06 +01:00
parent 9fbb449e06
commit 0ea64ad8ab
1 changed files with 7 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
tgt-vhdl/stmt.cc
View File

@ -193,9 +193,13 @@ static int draw_nbassign(vhdl_process *proc, stmt_container *container,
vhdl_expr *rhs = rhs_raw->cast(decl->get_type()); vhdl_expr *rhs = rhs_raw->cast(decl->get_type());
// If this is an `inital' process and we haven't yet // If this is an `inital' process and we haven't yet
// generated a `wait' statement then initializing the // generated a `wait' statement then this assignment
// signal here is equivalent to initializing to in the // needs to be moved to the declaration. Otherwise the
// declaration // Verilog behaviour won't be preserved: VHDL does not
// distinguish `initial' and `always' processes so an
// `always' process might be activatated before an
// `initial' process at time 0. The `always' process may
// then use the uninitialized signal value.
// The second test ensures that we only try to initialise // The second test ensures that we only try to initialise
// internal signals not ports // internal signals not ports
if (proc->is_initial() && ivl_signal_port(sig) == IVL_SIP_NONE) { if (proc->is_initial() && ivl_signal_port(sig) == IVL_SIP_NONE) {