Enable latch generation in synthesis.
(reworked patch supplied by Johann Klammer)
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81d3b7a25c
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0e537c5465
48
synth2.cc
48
synth2.cc
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@ -1581,28 +1581,44 @@ bool NetProcTop::synth_async(Design*des)
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bool flag = statement_->synth_async(des, scope(), nex_set, nex_out, enables, bitmasks);
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if (!flag) return false;
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bool latch_flag = false;
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for (unsigned idx = 0 ; idx < enables.pin_count() ; idx += 1) {
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if (!enables.pin(idx).is_linked(scope()->tie_hi())) {
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flag = tie_off_floating_inputs_(des, nex_set, nex_in, bitmasks, false);
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if (!flag) return false;
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for (unsigned idx = 0 ; idx < nex_set.size() ; idx += 1) {
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if (enables.pin(idx).is_linked(scope()->tie_hi())) {
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connect(nex_set[idx].lnk, nex_out.pin(idx));
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} else {
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cerr << get_fileline() << ": warning: "
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<< "A latch has been inferred for '"
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<< nex_set[idx].lnk.nexus()->pick_any_net()->name()
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<< "'." << endl;
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latch_flag = true;
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if (debug_synth2) {
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cerr << get_fileline() << ": debug: "
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<< "Top level making a "
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<< nex_set[idx].wid << "-wide "
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<< "NetLatch device." << endl;
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}
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NetLatch*latch = new NetLatch(scope(), scope()->local_symbol(),
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nex_set[idx].wid);
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des->add_node(latch);
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latch->set_line(*this);
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NetNet*tmp = nex_out.pin(idx).nexus()->pick_any_net();
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tmp->set_line(*this);
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assert(tmp);
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tmp = crop_to_width(des, tmp, latch->width());
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connect(nex_set[idx].lnk, latch->pin_Q());
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connect(tmp->pin(0), latch->pin_Data());
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assert (enables.pin(idx).is_linked());
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connect(enables.pin(idx), latch->pin_Enable());
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}
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}
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if (latch_flag) {
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cerr << get_fileline() << ": sorry: Latches are not "
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<< "currently supported in synthesis." << endl;
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des->errors += 1;
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return false;
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}
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flag = tie_off_floating_inputs_(des, nex_set, nex_in, bitmasks, false);
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if (!flag) return false;
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for (unsigned idx = 0 ; idx < nex_set.size() ; idx += 1)
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connect(nex_set[idx].lnk, nex_out.pin(idx));
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synthesized_design_ = des;
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return true;
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