vhdlpp: Turn on the reg_flag for types that cannot be packed.
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@ -244,6 +244,10 @@ int ExpAggregate::emit_array_(ostream&out, Entity*ent, Architecture*arc, const V
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// Emit the elements as a concatenation. This works great for
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// Emit the elements as a concatenation. This works great for
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// vectors of bits. We implement VHDL arrays as packed arrays,
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// vectors of bits. We implement VHDL arrays as packed arrays,
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// so this should be generally correct.
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// so this should be generally correct.
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// TODO uncomment this once ivl supports assignments of '{}
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/*if(!peek_type()->can_be_packed())
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out << "'";*/
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out << "{";
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out << "{";
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for (int64_t idx = use_msb ; idx >= use_lsb ; idx -= 1) {
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for (int64_t idx = use_msb ; idx >= use_lsb ; idx -= 1) {
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choice_element*cur = element_map[idx];
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choice_element*cur = element_map[idx];
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@ -68,7 +68,7 @@ int Signal::emit(ostream&out, Entity*ent, Architecture*arc)
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VType::decl_t decl;
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VType::decl_t decl;
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type_elaborate_(decl);
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type_elaborate_(decl);
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if (peek_refcnt_sequ_() > 0)
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if (peek_refcnt_sequ_() > 0 || !peek_type()->can_be_packed())
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decl.reg_flag = true;
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decl.reg_flag = true;
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errors += decl.emit(out, peek_name_());
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errors += decl.emit(out, peek_name_());
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@ -87,7 +87,7 @@ int Variable::emit(ostream&out, Entity*, Architecture*)
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VType::decl_t decl;
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VType::decl_t decl;
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type_elaborate_(decl);
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type_elaborate_(decl);
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if (peek_refcnt_sequ_() > 0)
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if (peek_refcnt_sequ_() > 0 || !peek_type()->can_be_packed())
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decl.reg_flag = true;
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decl.reg_flag = true;
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errors += decl.emit(out, peek_name_());
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errors += decl.emit(out, peek_name_());
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out << ";" << endl;
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out << ";" << endl;
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