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Changes to netlist.h 

Changes so "Microsoft Visual Studio Express 2015 RC Web" could build it without a bunch of runtime errors and crashes during regression testing.  When declaring an bitfield variable of type enum in a struct, the enum has to have an underlying integer type for MSVC++ when compiling a C++ file, and for these cases, it had to be unsigned integer for everything to work okay during regression testing.
This commit is contained in:
Frederick C. Kurz 2015-07-10 12:50:38 -04:00 committed by Stephen Williams
parent 82d46a5e1a
commit 093e7eb2c8
1 changed files with 12 additions and 0 deletions
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12
netlist.h
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@ -102,7 +102,11 @@ class Link {
friend class NexusSet; friend class NexusSet;
public: public:
#if defined(__cplusplus) && !defined(__GNUC__)
enum DIR : unsigned int { PASSIVE, INPUT, OUTPUT };
#else
enum DIR { PASSIVE, INPUT, OUTPUT }; enum DIR { PASSIVE, INPUT, OUTPUT };
#endif
private: // Only NetPins can create/delete Link objects private: // Only NetPins can create/delete Link objects
Link(); Link();
@ -619,7 +623,11 @@ class NetDelaySrc : public NetObj {
class PortType class PortType
{ {
public: public:
#if defined(__cplusplus) && !defined(__GNUC__)
enum Enum : unsigned int { NOT_A_PORT, PIMPLICIT, PINPUT, POUTPUT, PINOUT, PREF };
#else
enum Enum { NOT_A_PORT, PIMPLICIT, PINPUT, POUTPUT, PINOUT, PREF }; enum Enum { NOT_A_PORT, PIMPLICIT, PINPUT, POUTPUT, PINOUT, PREF };
#endif
/* /*
* Merge Port types (used to construct a sane combined port-type * Merge Port types (used to construct a sane combined port-type
@ -647,7 +655,11 @@ struct PortInfo
class NetNet : public NetObj, public PortType { class NetNet : public NetObj, public PortType {
public: public:
#if defined(__cplusplus) && !defined(__GNUC__)
enum Type : unsigned int { NONE, IMPLICIT, IMPLICIT_REG, INTEGER, WIRE, TRI, TRI1,
#else
enum Type { NONE, IMPLICIT, IMPLICIT_REG, INTEGER, WIRE, TRI, TRI1, enum Type { NONE, IMPLICIT, IMPLICIT_REG, INTEGER, WIRE, TRI, TRI1,
#endif
SUPPLY0, SUPPLY1, WAND, TRIAND, TRI0, WOR, TRIOR, REG, SUPPLY0, SUPPLY1, WAND, TRIAND, TRI0, WOR, TRIOR, REG,
UNRESOLVED_WIRE }; UNRESOLVED_WIRE };