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Rename signals that would be illegal VHDL names

This commit is contained in:
Nick Gasson 2008-06-19 16:15:47 +01:00
parent 6622b5fe3a
commit 08d80b35cb
1 changed files with 12 additions and 1 deletions
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13
tgt-vhdl/scope.cc
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@ -141,9 +141,20 @@ static void declare_signals(vhdl_arch *arch, ivl_scope_t scope)
remember_signal(sig, arch->get_parent()); remember_signal(sig, arch->get_parent());
// Make sure the signal name conforms to VHDL naming rules // Make sure the signal name conforms to VHDL naming rules
std::string name(ivl_signal_basename(sig)); std::string name(ivl_signal_basename(sig));
if (name[0] == '_') if (name[0] == '_')
name.insert(0, "VL"); name.insert(0, "VL");
const char *vhdl_reserved[] = {
"in", "out", "entity", "architecture", "inout", // Etc...
NULL
};
for (const char **p = vhdl_reserved; *p != NULL; p++) {
if (name == *p) {
name.insert(0, "VL_");
break;
}
}
rename_signal(sig, name.c_str()); rename_signal(sig, name.c_str());
ivl_signal_port_t mode = ivl_signal_port(sig); ivl_signal_port_t mode = ivl_signal_port(sig);