Handle repeat concatenation in continuous assign
When a repeat concatenation expression is translated to a netlist, get the repeat expression right. This comes up when an elab_and_eval elaboration contains a repeat concationation, and the expression is ultimately turned into a netlist by expr_synth. Signed-off-by: Stephen Williams <steve@icarus.com>
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Stephen Williams
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963b26283a
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191
expr_synth.cc
191
expr_synth.cc
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@ -561,13 +561,18 @@ NetNet* NetEConcat::synthesize(Design*des)
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osig->data_type(tmp[0]->data_type());
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osig->data_type(tmp[0]->data_type());
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NetConcat*concat = new NetConcat(scope, scope->local_symbol(),
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NetConcat*concat = new NetConcat(scope, scope->local_symbol(),
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osig->vector_width(), parms_.count());
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osig->vector_width(),
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parms_.count() * repeat());
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concat->set_line(*this);
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concat->set_line(*this);
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des->add_node(concat);
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des->add_node(concat);
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connect(concat->pin(0), osig->pin(0));
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connect(concat->pin(0), osig->pin(0));
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for (unsigned idx = 0 ; idx < parms_.count() ; idx += 1) {
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unsigned cur_pin = 1;
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connect(concat->pin(idx+1), tmp[parms_.count()-idx-1]->pin(0));
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for (unsigned rpt = 0; rpt < repeat(); rpt += 1) {
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for (unsigned idx = 0 ; idx < parms_.count() ; idx += 1) {
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connect(concat->pin(cur_pin), tmp[parms_.count()-idx-1]->pin(0));
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cur_pin += 1;
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}
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}
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}
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delete[]tmp;
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delete[]tmp;
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@ -868,183 +873,3 @@ NetNet* NetESignal::synthesize(Design*des)
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return net_;
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return net_;
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}
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}
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/*
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* $Log: expr_synth.cc,v $
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* Revision 1.87 2007/06/02 03:42:12 steve
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* Properly evaluate scope path expressions.
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*
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* Revision 1.86 2007/04/15 01:37:29 steve
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* Allow bit/part select of vectors in continuous assignments.
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*
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* Revision 1.85 2007/04/12 05:21:54 steve
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* fix handling of unary reduction logic in certain nets.
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*
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* Revision 1.84 2007/04/04 02:31:57 steve
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* Remove useless assert
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*
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* Revision 1.83 2007/02/05 01:42:31 steve
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* Set some missing local flags.
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*
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* Revision 1.82 2007/01/20 02:10:45 steve
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* Get argument widths right for shift results.
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*
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* Revision 1.81 2007/01/16 05:44:15 steve
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* Major rework of array handling. Memories are replaced with the
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* more general concept of arrays. The NetMemory and NetEMemory
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* classes are removed from the ivl core program, and the IVL_LPM_RAM
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* lpm type is removed from the ivl_target API.
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*
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* Revision 1.80 2006/08/08 05:11:37 steve
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* Handle 64bit delay constants.
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*
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* Revision 1.79 2006/07/31 03:50:17 steve
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* Add support for power in constant expressions.
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*
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* Revision 1.78 2006/07/08 21:48:46 steve
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* Handle real valued literals in net contexts.
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*
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* Revision 1.77 2006/05/01 20:47:59 steve
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* More explicit datatype setup.
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*
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* Revision 1.76 2006/05/01 05:40:21 steve
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* fix net type of multiply output.
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*
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* Revision 1.75 2006/04/30 05:17:48 steve
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* Get the data type of part select results right.
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*
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* Revision 1.74 2006/01/03 05:15:33 steve
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* Fix the return type of a synthesized divide.
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*
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* Revision 1.73 2005/09/15 23:04:09 steve
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* Make sure div, mod and mult nodes have line number info.
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*
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* Revision 1.72 2005/08/31 05:07:31 steve
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* Handle memory references is continuous assignments.
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*
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* Revision 1.71 2005/06/13 23:22:14 steve
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* use NetPartSelect to shrink part from high bits.
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*
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* Revision 1.70 2005/06/13 22:26:03 steve
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* Make synthesized padding vector-aware.
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*
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* Revision 1.69 2005/05/15 04:47:00 steve
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* synthesis of Logic and shifts using vector gates.
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*
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* Revision 1.68 2005/05/06 00:25:13 steve
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* Handle synthesis of concatenation expressions.
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*
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* Revision 1.67 2005/04/25 01:30:31 steve
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* synthesis of add and unary get vector widths right.
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*
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* Revision 1.66 2005/04/24 23:44:02 steve
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* Update DFF support to new data flow.
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*
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* Revision 1.65 2005/03/12 06:43:35 steve
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* Update support for LPM_MOD.
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*
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* Revision 1.64 2005/02/19 02:43:38 steve
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* Support shifts and divide.
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*
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* Revision 1.63 2005/02/12 06:25:40 steve
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* Restructure NetMux devices to pass vectors.
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* Generate NetMux devices from ternary expressions,
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* Reduce NetMux devices to bufif when appropriate.
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*
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* Revision 1.62 2005/01/28 05:39:33 steve
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* Simplified NetMult and IVL_LPM_MULT.
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*
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* Revision 1.61 2005/01/16 04:20:32 steve
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* Implement LPM_COMPARE nodes as two-input vector functors.
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*
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* Revision 1.60 2004/12/11 02:31:26 steve
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* Rework of internals to carry vectors through nexus instead
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* of single bits. Make the ivl, tgt-vvp and vvp initial changes
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* down this path.
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*
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* Revision 1.59 2004/06/30 02:16:26 steve
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* Implement signed divide and signed right shift in nets.
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*
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* Revision 1.58 2004/06/16 16:21:34 steve
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* Connect rsif of multiply to DataB.
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*
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* Revision 1.57 2004/06/12 15:00:02 steve
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* Support / and % in synthesized contexts.
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*
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* Revision 1.56 2004/06/01 01:04:57 steve
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* Fix synthesis method for logical and/or
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*
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* Revision 1.55 2004/02/20 18:53:35 steve
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* Addtrbute keys are perm_strings.
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*
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* Revision 1.54 2004/02/18 17:11:56 steve
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* Use perm_strings for named langiage items.
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*
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* Revision 1.53 2004/02/15 04:23:48 steve
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* Fix evaluation of compare to constant expression.
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*
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* Revision 1.52 2003/11/10 19:39:20 steve
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* Remove redundant scope tokens.
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*
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* Revision 1.51 2003/10/27 06:04:21 steve
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* More flexible width handling for synthesized add.
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*
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* Revision 1.50 2003/09/26 02:44:27 steve
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* Assure ternary arguments are wide enough.
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*
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* Revision 1.49 2003/09/03 23:31:36 steve
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* Support synthesis of constant downshifts.
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*
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* Revision 1.48 2003/08/28 04:11:18 steve
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* Spelling patch.
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*
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* Revision 1.47 2003/08/09 03:23:40 steve
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* Add support for IVL_LPM_MULT device.
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*
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* Revision 1.46 2003/07/26 03:34:42 steve
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* Start handling pad of expressions in code generators.
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*
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* Revision 1.45 2003/06/24 01:38:02 steve
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* Various warnings fixed.
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*
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* Revision 1.44 2003/04/19 04:52:56 steve
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* Less picky about expression widths while synthesizing ternary.
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*
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* Revision 1.43 2003/04/08 05:07:15 steve
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* Detect constant shift distances in synthesis.
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*
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* Revision 1.42 2003/04/08 04:33:55 steve
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* Synthesize shift expressions.
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*
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* Revision 1.41 2003/03/06 00:28:41 steve
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* All NetObj objects have lex_string base names.
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*
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* Revision 1.40 2003/02/26 01:29:24 steve
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* LPM objects store only their base names.
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*
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* Revision 1.39 2003/01/30 16:23:07 steve
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* Spelling fixes.
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*
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* Revision 1.38 2003/01/26 21:15:58 steve
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* Rework expression parsing and elaboration to
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* accommodate real/realtime values and expressions.
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*
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* Revision 1.37 2002/11/17 23:37:55 steve
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* Magnitude compare to 0.
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*
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* Revision 1.36 2002/08/12 01:34:59 steve
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* conditional ident string using autoconfig.
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*
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* Revision 1.35 2002/07/07 22:31:39 steve
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* Smart synthesis of binary AND expressions.
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*
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* Revision 1.34 2002/07/05 21:26:17 steve
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* Avoid emitting to vvp local net symbols.
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*
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* Revision 1.33 2002/05/26 01:39:02 steve
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* Carry Verilog 2001 attributes with processes,
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* all the way through to the ivl_target API.
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*
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* Divide signal reference counts between rval
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* and lval references.
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*/
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