luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

print reg signals.

This commit is contained in:
steve 2000-10-04 02:24:20 +00:00
parent 2f668421a3
commit 07aa86f0fa
1 changed files with 8 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
tgt-verilog/verilog.c
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT) && !defined(macintosh)
#ident "$Id: verilog.c,v 1.5 2000/09/30 02:18:15 steve Exp $"
#ident "$Id: verilog.c,v 1.6 2000/10/04 02:24:20 steve Exp $"
#endif
/*
@ -113,6 +113,10 @@ int target_net_signal(const char*name, ivl_signal_t net)
switch (ivl_signal_type(net)) {
case IVL_SIT_REG:
fprintf(out, " reg [%u:0] %s;\n", cnt-1, name);
break;
case IVL_SIT_WIRE:
fprintf(out, " wire [%u:0] %s;\n", cnt-1, name);
break;
@ -263,6 +267,9 @@ int target_process(ivl_process_t net)
/*
* $Log: verilog.c,v $
* Revision 1.6 2000/10/04 02:24:20 steve
* print reg signals.
*
* Revision 1.5 2000/09/30 02:18:15 steve
* ivl_expr_t support for binary operators,
* Create a proper ivl_scope_t object.