Remove some dead code in tgt-vvp.
This commit is contained in:
Stephen Williams
parent
1905264061
commit
079065ea73
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@ -414,6 +414,7 @@ static struct vector_info draw_eq_immediate(ivl_expr_t expr, unsigned ewid,
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* This handles the special case that the operands of the comparison
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* are real valued expressions.
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*/
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#if 0
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static struct vector_info draw_binary_expr_eq_real(ivl_expr_t expr)
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{
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struct vector_info res;
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@ -443,6 +444,15 @@ static struct vector_info draw_binary_expr_eq_real(ivl_expr_t expr)
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return res;
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}
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#else
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static struct vector_info draw_binary_expr_eq_real(ivl_expr_t expr)
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{
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struct vector_info res = {0, 0};
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fprintf(vvp_out, " ; draw_binary_expr_real: dead code\n");
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vvp_errors += 1;
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return res;
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}
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#endif
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static struct vector_info draw_binary_expr_eq_string(ivl_expr_t expr)
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{
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@ -753,117 +763,6 @@ static struct vector_info draw_binary_expr_land(ivl_expr_t expr, unsigned wid)
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return lv;
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}
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static struct vector_info draw_binary_expr_lor(ivl_expr_t expr, unsigned wid,
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int stuff_ok_flag)
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{
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ivl_expr_t le = ivl_expr_oper1(expr);
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ivl_expr_t re = ivl_expr_oper2(expr);
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struct vector_info lv;
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struct vector_info rv;
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lv = draw_eval_expr(le, STUFF_OK_XZ);
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/* if the left operand has width, then evaluate the single-bit
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logical equivalent. */
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if ((lv.base >= 4) && (lv.wid > 1)) {
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struct vector_info tmp;
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clr_vector(lv);
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tmp.base = allocate_vector(1);
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tmp.wid = 1;
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assert(tmp.base);
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fprintf(vvp_out, " %%or/r %u, %u, %u;\n", tmp.base,
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lv.base, lv.wid);
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lv = tmp;
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}
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/* The right expression may be left in registers 4-7 because
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I'll be using it immediately. */
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rv = draw_eval_expr(re, STUFF_OK_XZ|STUFF_OK_47);
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/* if the right operand has width, then evaluate the single-bit
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logical equivalent. */
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if ((rv.base >= 4) && (rv.wid > 1)) {
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struct vector_info tmp;
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clr_vector(rv);
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tmp.base = allocate_vector(1);
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tmp.wid = 1;
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assert(tmp.base);
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fprintf(vvp_out, " %%or/r %u, %u, %u;\n", tmp.base,
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rv.base, rv.wid);
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rv = tmp;
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}
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if (lv.base < 4) {
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if (rv.base < 4) {
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unsigned lb = lv.base;
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unsigned rb = rv.base;
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if ((lb == 0) && (rb == 0)) {
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lv.base = 0;
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} else if ((lb == 1) || (rb == 1)) {
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lv.base = 1;
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} else {
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lv.base = 2;
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}
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} else if (lv.base==0) {
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lv = rv;
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} else {
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fprintf(vvp_out, " %%or %u, %u, 1;\n", rv.base, lv.base);
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lv = rv;
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}
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} else if (rv.base == 0) {
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; /* Just return lv. */
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} else {
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if (rv.base >= 8 && lv.base < 8 && !(stuff_ok_flag&STUFF_OK_47)) {
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/* If STUFF_OK_47 is false, and rv is not in the
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47 area (and lv is) then plan to or the result
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into the rv instead. This can case a %mov later. */
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struct vector_info tmp = lv;
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lv = rv;
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rv = tmp;
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}
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fprintf(vvp_out, " %%or %u, %u, 1;\n", lv.base, rv.base);
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if (rv.base >= 8) clr_vector(rv);
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}
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if (wid==1 && (lv.base<4 || lv.base>=8 || (stuff_ok_flag&STUFF_OK_47)))
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return lv;
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/* If we only want the single bit result, then we are done. */
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if (wid == 1) {
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if (lv.base >= 4 && lv.base < 8) {
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unsigned tmp = allocate_vector(1);
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fprintf(vvp_out, " %%mov %u, %u, 1;\n", tmp, lv.base);
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lv.base = tmp;
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}
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return lv;
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}
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/* Write the result into a zero-padded result. */
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{ unsigned base = allocate_vector(wid);
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if (base == 0) {
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fprintf(stderr, "%s:%u: vvp.tgt error: "
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"Unable to allocate %u thread bits "
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"for result of padded logical OR.\n",
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ivl_expr_file(expr), ivl_expr_lineno(expr), wid);
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vvp_errors += 1;
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}
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fprintf(vvp_out, " %%mov %u, %u, 1;\n", base, lv.base);
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if (lv.base >= 8) clr_vector(lv);
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lv.base = base;
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lv.wid = wid;
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fprintf(vvp_out, " %%pad %u, 0, %u;\n", base+1, wid-1);
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}
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return lv;
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}
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static struct vector_info draw_binary_expr_le_real(ivl_expr_t expr)
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{
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struct vector_info res;
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@ -1181,423 +1080,6 @@ static struct vector_info draw_binary_expr_le(ivl_expr_t expr,
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return lv;
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}
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static struct vector_info draw_logic_immediate(ivl_expr_t expr,
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ivl_expr_t le,
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ivl_expr_t re,
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unsigned wid)
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{
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struct vector_info lv = draw_eval_expr_wid(le, wid, STUFF_OK_XZ);
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assert(number_is_immediate(re, IMM_WID, 0));
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assert(! number_is_unknown(re));
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unsigned long imm = get_number_immediate(re);
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assert(lv.base >= 4);
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switch (ivl_expr_opcode(expr)) {
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case '&':
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fprintf(vvp_out, " %%andi %u, %lu, %u;\n", lv.base, imm, lv.wid);
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break;
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default:
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assert(0);
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break;
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}
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return lv;
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}
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static struct vector_info draw_binary_expr_logic(ivl_expr_t expr,
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unsigned wid)
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{
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ivl_expr_t le = ivl_expr_oper1(expr);
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ivl_expr_t re = ivl_expr_oper2(expr);
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struct vector_info lv;
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struct vector_info rv;
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if (ivl_expr_opcode(expr) == '&') {
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if (number_is_immediate(re, IMM_WID, 0) && !number_is_unknown(re))
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return draw_logic_immediate(expr, le, re, wid);
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if (number_is_immediate(le, IMM_WID, 0) && !number_is_unknown(le))
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return draw_logic_immediate(expr, re, le, wid);
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}
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lv = draw_eval_expr_wid(le, wid, STUFF_OK_XZ);
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rv = draw_eval_expr_wid(re, wid, STUFF_OK_XZ);
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/* The result goes into the left operand, and that is returned
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as the result. The instructions do not allow the lv value
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to be a constant bit, so we either switch the operands, or
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copy the vector into a new area. */
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if (lv.base < 4) {
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if (rv.base > 4) {
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struct vector_info tmp = lv;
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lv = rv;
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rv = tmp;
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} else {
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struct vector_info tmp;
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tmp.base = allocate_vector(lv.wid);
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tmp.wid = lv.wid;
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if (tmp.base == 0) {
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fprintf(stderr, "%s:%u: vvp.tgt error: "
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"Unable to allocate %u thread bits "
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"for result of binary logic.\n",
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ivl_expr_file(expr), ivl_expr_lineno(expr),
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wid);
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vvp_errors += 1;
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}
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fprintf(vvp_out, " %%mov %u, %u, %u;\n",
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tmp.base, lv.base, tmp.wid);
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lv = tmp;
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}
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}
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switch (ivl_expr_opcode(expr)) {
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case '&':
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fprintf(vvp_out, " %%and %u, %u, %u;\n",
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lv.base, rv.base, wid);
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break;
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case '|':
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fprintf(vvp_out, " %%or %u, %u, %u;\n",
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lv.base, rv.base, wid);
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break;
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case '^':
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fprintf(vvp_out, " %%xor %u, %u, %u;\n",
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lv.base, rv.base, wid);
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break;
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case 'A': /* NAND (~&) */
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fprintf(vvp_out, " %%nand %u, %u, %u;\n",
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lv.base, rv.base, wid);
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break;
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case 'O': /* NOR (~|) */
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fprintf(vvp_out, " %%nor %u, %u, %u;\n",
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lv.base, rv.base, wid);
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break;
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case 'X': /* exclusive nor (~^) */
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fprintf(vvp_out, " %%xnor %u, %u, %u;\n",
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lv.base, rv.base, wid);
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break;
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default:
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assert(0);
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}
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clr_vector(rv);
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return lv;
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}
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static struct vector_info draw_load_add_immediate(ivl_expr_t le,
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ivl_expr_t re,
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unsigned wid,
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int signed_flag)
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{
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struct vector_info lv;
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long imm;
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assert(! number_is_unknown(re));
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assert(number_is_immediate(re, IMM_WID, 1));
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imm = get_number_immediate(re);
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lv.base = allocate_vector(wid);
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lv.wid = wid;
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if (lv.base == 0) {
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fprintf(stderr, "%s:%u: vvp.tgt error: "
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"Unable to allocate %u thread bits "
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"for result of addition.\n",
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ivl_expr_file(le), ivl_expr_lineno(le), wid);
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vvp_errors += 1;
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}
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/* Load the signal value with a %load that adds the index
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register to the value being loaded. */
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draw_signal_dest(le, lv, signed_flag, imm);
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return lv;
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}
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static struct vector_info draw_add_immediate(ivl_expr_t le,
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ivl_expr_t re,
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unsigned wid)
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{
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struct vector_info lv;
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unsigned long imm;
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lv = draw_eval_expr_wid(le, wid, STUFF_OK_XZ);
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assert(lv.wid == wid);
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assert(! number_is_unknown(re));
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assert(number_is_immediate(re, IMM_WID, 0));
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imm = get_number_immediate(re);
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/* This shouldn't generally happen, because the elaborator
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should take care of simple constant propagation like this,
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but it doesn't have to and it is easy to catch here. */
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if (imm == 0)
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return lv;
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switch (lv.base) {
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case 0: /* Left expression is 0. */
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lv.base = allocate_vector(wid);
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if (lv.base == 0) {
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fprintf(stderr, "%s:%u: vvp.tgt error: "
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"Unable to allocate %u thread bits "
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"for result of addition.\n",
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ivl_expr_file(re), ivl_expr_lineno(re), wid);
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vvp_errors += 1;
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}
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fprintf(vvp_out, " %%movi %u, %lu %u;\n", lv.base, imm, wid);
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break;
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case 1: /* Left expression is 1...1 (i.e. -1) */
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imm -= 1;
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if (imm == 0) {
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lv.base = 0;
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} else {
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lv.base = allocate_vector(wid);
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if (lv.base == 0) {
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fprintf(stderr, "%s:%u: vvp.tgt error: "
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"Unable to allocate %u thread bits "
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"for result of addition.\n",
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ivl_expr_file(re), ivl_expr_lineno(re), wid);
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vvp_errors += 1;
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}
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fprintf(vvp_out, " %%movi %u, %lu %u;\n", lv.base, imm, wid);
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}
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break;
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case 2: /* Left expression is 'bx or 'bz */
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case 3:
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lv.base = 2;
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break;
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default: /* The regular case. */
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fprintf(vvp_out, " %%addi %u, %lu, %u;\n", lv.base, imm, wid);
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break;
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}
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return lv;
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}
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/*
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* The subi is restricted to imm operands that are <= 16 bits wide.
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*/
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static struct vector_info draw_sub_immediate(ivl_expr_t le,
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ivl_expr_t re,
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unsigned wid)
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{
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struct vector_info lv;
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unsigned long imm;
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unsigned tmp;
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lv = draw_eval_expr_wid(le, wid, STUFF_OK_XZ);
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assert(lv.wid == wid);
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assert(! number_is_unknown(re));
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assert(number_is_immediate(re, IMM_WID, 0));
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imm = get_number_immediate(re);
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if (imm == 0)
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return lv;
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switch (lv.base) {
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case 0:
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case 1:
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tmp = allocate_vector(wid);
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if (tmp == 0) {
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fprintf(stderr, "%s:%u: vvp.tgt error: "
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"Unable to allocate %u thread bits "
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"for result of subtraction.\n",
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ivl_expr_file(le), ivl_expr_lineno(le), wid);
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vvp_errors += 1;
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}
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fprintf(vvp_out, " %%mov %u, %u, %u;\n", tmp, lv.base, wid);
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lv.base = tmp;
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fprintf(vvp_out, " %%subi %u, %lu, %u;\n", lv.base, imm, wid);
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break;
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case 2:
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case 3:
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lv.base = 2;
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break;
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default:
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fprintf(vvp_out, " %%subi %u, %lu, %u;\n", lv.base, imm, wid);
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break;
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}
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return lv;
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}
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static struct vector_info draw_mul_immediate(ivl_expr_t le,
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ivl_expr_t re,
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unsigned wid)
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{
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struct vector_info lv;
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unsigned long imm;
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lv = draw_eval_expr_wid(le, wid, STUFF_OK_XZ);
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assert(lv.wid == wid);
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assert(! number_is_unknown(re));
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assert(number_is_immediate(re, IMM_WID, 0));
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imm = get_number_immediate(re);
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if (imm == 0)
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return lv;
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fprintf(vvp_out, " %%muli %u, %lu, %u;\n", lv.base, imm, lv.wid);
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return lv;
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}
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static struct vector_info draw_binary_expr_arith(ivl_expr_t expr, unsigned wid)
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{
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ivl_expr_t le = ivl_expr_oper1(expr);
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ivl_expr_t re = ivl_expr_oper2(expr);
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struct vector_info lv;
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struct vector_info rv;
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int signed_flag = ivl_expr_signed(le) && ivl_expr_signed(re) ? 1 : 0;
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const char*sign_string = signed_flag ? "/s" : "";
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if ((ivl_expr_opcode(expr) == '+')
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&& (ivl_expr_type(le) == IVL_EX_SIGNAL)
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&& (ivl_expr_type(re) == IVL_EX_ULONG)
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&& number_is_immediate(re, IMM_WID, 1))
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return draw_load_add_immediate(le, re, wid, signed_flag);
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if ((ivl_expr_opcode(expr) == '+')
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&& (ivl_expr_type(le) == IVL_EX_SIGNAL)
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&& (ivl_expr_type(re) == IVL_EX_NUMBER)
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&& (! number_is_unknown(re))
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&& number_is_immediate(re, IMM_WID, 1))
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return draw_load_add_immediate(le, re, wid, signed_flag);
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if ((ivl_expr_opcode(expr) == '+')
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&& (ivl_expr_type(re) == IVL_EX_SIGNAL)
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&& (ivl_expr_type(le) == IVL_EX_ULONG)
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&& number_is_immediate(re, IMM_WID, 1))
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return draw_load_add_immediate(re, le, wid, signed_flag);
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if ((ivl_expr_opcode(expr) == '+')
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&& (ivl_expr_type(re) == IVL_EX_SIGNAL)
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&& (ivl_expr_type(le) == IVL_EX_NUMBER)
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&& (! number_is_unknown(le))
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&& number_is_immediate(le, IMM_WID, 1))
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return draw_load_add_immediate(re, le, wid, signed_flag);
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if ((ivl_expr_opcode(expr) == '+')
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&& (ivl_expr_type(re) == IVL_EX_ULONG)
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&& number_is_immediate(re, IMM_WID, 0))
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return draw_add_immediate(le, re, wid);
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if ((ivl_expr_opcode(expr) == '+')
|
||||
&& (ivl_expr_type(re) == IVL_EX_NUMBER)
|
||||
&& (! number_is_unknown(re))
|
||||
&& number_is_immediate(re, IMM_WID, 0))
|
||||
return draw_add_immediate(le, re, wid);
|
||||
|
||||
if ((ivl_expr_opcode(expr) == '-')
|
||||
&& (ivl_expr_type(re) == IVL_EX_ULONG)
|
||||
&& number_is_immediate(re, IMM_WID, 0))
|
||||
return draw_sub_immediate(le, re, wid);
|
||||
|
||||
if ((ivl_expr_opcode(expr) == '-')
|
||||
&& (ivl_expr_type(re) == IVL_EX_NUMBER)
|
||||
&& (! number_is_unknown(re))
|
||||
&& number_is_immediate(re, IMM_WID, 0))
|
||||
return draw_sub_immediate(le, re, wid);
|
||||
|
||||
if ((ivl_expr_opcode(expr) == '*')
|
||||
&& (ivl_expr_type(re) == IVL_EX_NUMBER)
|
||||
&& (! number_is_unknown(re))
|
||||
&& number_is_immediate(re, IMM_WID, 0))
|
||||
return draw_mul_immediate(le, re, wid);
|
||||
|
||||
lv = draw_eval_expr_wid(le, wid, STUFF_OK_XZ);
|
||||
rv = draw_eval_expr_wid(re, wid, STUFF_OK_XZ|STUFF_OK_RO);
|
||||
|
||||
if (lv.wid != wid) {
|
||||
fprintf(stderr, "XXXX ivl_expr_opcode(expr) = %c,"
|
||||
" lv.wid=%u, wid=%u\n", ivl_expr_opcode(expr),
|
||||
lv.wid, wid);
|
||||
}
|
||||
|
||||
assert(lv.wid == wid);
|
||||
assert(rv.wid == wid);
|
||||
|
||||
/* The arithmetic instructions replace the left operand with
|
||||
the result. If the left operand is a replicated constant,
|
||||
then I need to make a writable copy so that the
|
||||
instruction can operate. */
|
||||
if (lv.base < 4) {
|
||||
struct vector_info tmp;
|
||||
|
||||
tmp.base = allocate_vector(wid);
|
||||
tmp.wid = wid;
|
||||
if (tmp.base == 0) {
|
||||
fprintf(stderr, "%s:%u: vvp.tgt error: "
|
||||
"Unable to allocate %u thread bits "
|
||||
"for result of arithmetic expression.\n",
|
||||
ivl_expr_file(expr), ivl_expr_lineno(expr), wid);
|
||||
vvp_errors += 1;
|
||||
}
|
||||
|
||||
fprintf(vvp_out, " %%mov %u, %u, %u;\n", tmp.base,
|
||||
lv.base, wid);
|
||||
lv = tmp;
|
||||
}
|
||||
|
||||
switch (ivl_expr_opcode(expr)) {
|
||||
case '+':
|
||||
fprintf(vvp_out, " %%add %u, %u, %u;\n", lv.base, rv.base, wid);
|
||||
break;
|
||||
|
||||
case '-':
|
||||
fprintf(vvp_out, " %%sub %u, %u, %u;\n", lv.base, rv.base, wid);
|
||||
break;
|
||||
|
||||
case '*':
|
||||
fprintf(vvp_out, " %%mul %u, %u, %u;\n", lv.base, rv.base, wid);
|
||||
break;
|
||||
|
||||
case '/':
|
||||
fprintf(vvp_out, " %%div%s %u, %u, %u;\n", sign_string,
|
||||
lv.base, rv.base, wid);
|
||||
break;
|
||||
|
||||
case '%':
|
||||
fprintf(vvp_out, " %%mod%s %u, %u, %u;\n", sign_string,
|
||||
lv.base, rv.base, wid);
|
||||
break;
|
||||
|
||||
case 'p':
|
||||
if (ivl_expr_signed(le) || ivl_expr_signed(re)) {
|
||||
fprintf(vvp_out, " %%pow/s %u, %u, %u;\n",
|
||||
lv.base, rv.base, wid);
|
||||
} else {
|
||||
fprintf(vvp_out, " %%pow %u, %u, %u;\n",
|
||||
lv.base, rv.base, wid);
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
assert(0);
|
||||
}
|
||||
|
||||
clr_vector(rv);
|
||||
|
||||
return lv;
|
||||
}
|
||||
|
||||
static struct vector_info draw_binary_expr(ivl_expr_t expr,
|
||||
unsigned wid,
|
||||
int stuff_ok_flag)
|
||||
|
|
@ -1626,29 +1108,6 @@ static struct vector_info draw_binary_expr(ivl_expr_t expr,
|
|||
stuff_ok_used_flag = 1;
|
||||
break;
|
||||
|
||||
case '+':
|
||||
case '-':
|
||||
case '*':
|
||||
case '/':
|
||||
case '%':
|
||||
case 'p':
|
||||
rv = draw_binary_expr_arith(expr, wid);
|
||||
break;
|
||||
|
||||
case 'o': /* || (logical or) */
|
||||
rv = draw_binary_expr_lor(expr, wid, stuff_ok_flag);
|
||||
stuff_ok_used_flag = 1;
|
||||
break;
|
||||
|
||||
case '&':
|
||||
case '|':
|
||||
case '^':
|
||||
case 'A': /* NAND (~&) */
|
||||
case 'O': /* NOR (~|) */
|
||||
case 'X': /* XNOR (~^) */
|
||||
rv = draw_binary_expr_logic(expr, wid);
|
||||
break;
|
||||
|
||||
default:
|
||||
fprintf(stderr, "vvp.tgt error: draw_binary_expr: unsupported binary (%c)\n",
|
||||
ivl_expr_opcode(expr));
|
||||
|
|
|
|||
Loading…
Reference in New Issue