109 lines
3.1 KiB
C++
109 lines
3.1 KiB
C++
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/*
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* VHDL code generation for scopes.
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*
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* Copyright (C) 2008 Nick Gasson (nick@nickg.me.uk)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#include "vhdl_target.h"
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#include "vhdl_element.hh"
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#include <iostream>
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#include <sstream>
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#include <cassert>
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/*
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* Create a VHDL entity for scopes of type IVL_SCT_MODULE.
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*/
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static vhdl_entity *create_entity_for(ivl_scope_t scope)
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{
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assert(ivl_scope_type(scope) == IVL_SCT_MODULE);
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// The type name will become the entity name
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const char *tname = ivl_scope_tname(scope);
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// Verilog does not have the entity/architecture distinction
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// so we always create a pair and associate the architecture
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// with the entity for convenience (this also means that we
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// retain a 1-to-1 mapping of scope to VHDL element)
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vhdl_arch *arch = new vhdl_arch(tname);
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vhdl_entity *ent = new vhdl_entity(tname, arch);
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// Build a comment to add to the entity/architecture
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std::ostringstream ss;
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ss << "Generated from " << ivl_scope_name(scope);
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ss << " (" << ivl_scope_def_file(scope) << ":";
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ss << ivl_scope_def_lineno(scope) << ")";
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arch->set_comment(ss.str());
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ent->set_comment(ss.str());
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remember_entity(ent);
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return ent;
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}
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/*
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* Instantiate an entity in the hierarchy, and possibly create
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* that entity if it hasn't been encountered yet.
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*/
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static int draw_module(ivl_scope_t scope, ivl_scope_t parent)
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{
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assert(ivl_scope_type(scope) == IVL_SCT_MODULE);
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vhdl_entity *ent = find_entity(ivl_scope_tname(scope));
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if (NULL == ent)
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ent = create_entity_for(scope);
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assert(ent);
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if (parent != NULL) {
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std::cout << "parent " << ivl_scope_name(parent) << std::endl;
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}
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return 0;
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}
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int draw_scope(ivl_scope_t scope, void *_parent)
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{
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ivl_scope_t parent = static_cast<ivl_scope_t>(_parent);
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const char *name = ivl_scope_name(scope);
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const char *basename = ivl_scope_basename(scope);
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std::cout << "scope " << name << " (" << basename << ")" << std::endl;
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ivl_scope_type_t type = ivl_scope_type(scope);
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int rc = 0;
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switch (type) {
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case IVL_SCT_MODULE:
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rc = draw_module(scope, parent);
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break;
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default:
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error("No VHDL conversion for %s (at %s)",
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ivl_scope_tname(scope),
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ivl_scope_name(scope));
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break;
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}
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if (rc != 0)
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return rc;
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rc = ivl_scope_children(scope, draw_scope, scope);
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if (rc != 0)
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return rc;
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return 0;
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}
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