mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-09-07 11:51:38 +02:00
19 lines
296 B
Verilog
19 lines
296 B
Verilog
|
// Check that it is possible to declare an enum type with the integer type as
|
||
|
|
// the base type.
|
||
|
|
|
||
|
|
module test;
|
||
|
|
|
||
|
|
enum integer {
|
||
|
|
A
|
||
|
|
} E;
|
||
|
|
|
||
|
|
initial begin
|
||
|
|
if ($bits(E) == $bits(integer)) begin
|
||
|
|
$display("PASSED");
|
||
|
|
end else begin
|
||
|
|
$display("FAILED");
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
endmodule
|