93 lines
3.4 KiB
Plaintext
93 lines
3.4 KiB
Plaintext
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For those of you who wish to use Icarus Verilog, in combination with
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the Xilinx back end (Foundation or Alliance), it can be done. I have
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run some admittedly simple (no arithmetic, 600 equivalent gates) designs
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through this setup, targeting a Spartan XCS10.
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Verilog:
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As of Icarus Verilog 19990814, you still can't have logic buried
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in procedural (flip-flop) assignment. I use a hacked workaround
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copy of ivl that allows 1-bit wide logic. The other approach
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is to use temporary wires, assign them to the logic, and assign
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the reg to that wire. For example, instead of
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always @ (posedge Clk) Z = ~Q1 & ~Q2 & ~Q3 & ~Q4;
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you can write
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wire newZ;
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assign newZ = ~Q1 & ~Q2 & ~Q3 & ~Q4;
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always @ (posedge Clk) Z = newZ;
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Procedural assignments have to be given one at a time, to be
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"found" by xnfsyn. Say
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always @ (posedge Clk) Y = newY;
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always @ (posedge Clk) Z = newZ;
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rather than
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always @ (posedge Clk) begin
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Y = newY;
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Z = newZ;
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end
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I had reason to use a global clock net. I used this snippet of
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Verilog code to make it happen:
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primitive BUFG ( O, I );
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output O;
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input I;
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table
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0:0;
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1:1;
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endtable
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endprimitive
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$attribute(BUFG,"XNF-LCA","BUFG:O,I")
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Oh, yes, you probably also want to choose I/O pins! Try this:
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wire d1;
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$attribute(d1, "PAD", "i45"); // input
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wire vsync;
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$attribute(vsync, "PAD", "o67"); // output
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Running ivl:
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The -F switches are important. The following order seems to robustly
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generate valid XNF files:
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-Fxnfio -Fnobufz -Fsigfold -Fxnfsyn
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Generating .pcf files:
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The ngdbuild step seems to lose pin placement information that ivl
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puts in the XNF file. Use xnf2pcf to extract this information to
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a .pcf file, which the Xilinx place-and-route software _will_ pay
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attention to.
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Running the Xilinx back end:
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You can presumably use the GUI, but that doesn't fit in Makefiles :-).
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Here is the command sequence in pseudo-shell-script:
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ngdbuild -p $part $1.xnf $1.ngd
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map -p $part -o map.ncd $1.ngd
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xnf2pcf <$1.xnf >$1.pcf # see above
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par -w -ol 2 -d 0 map.ncd $1.ncd $1.pcf
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bitgen_flags = -g ConfigRate:SLOW -g TdoPin:PULLNONE -g DonePin:PULLUP \
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-g CRC:enable -g StartUpClk:CCLK -g SyncToDone:no \
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-g DoneActive:C1 -g OutputsActive:C3 -g GSRInactive:C4 \
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-g ReadClk:CCLK -g ReadCapture:enable -g ReadAbort:disable
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bitgen $1.ncd -l -w $bitgen_flags
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The Xilinx software has diarrhea of the temp files (14, not including
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.xnf, .pcf, .ngd, .ncd, and .bit), so this sequence is best done in a
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dedicated directory. Note in particular that map.ncd is a generic name.
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Downloading:
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I use the XESS (http://www.xess.com/) XSP-10 development board, which
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uses the PC parallel (printer) port for downloading and interaction
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with the host. They made an old version of their download program
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public domain, posted it at
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http://www.xess.com/FPGA/xstools.zip ,
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and now there is a Linux port at
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ftp://ftp.microux.com/pub/pilotscope/xstools.tar.gz .
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The above hints are based on my experience with Foundation 1.5 on NT
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(gack) and Alliance 2.1i on Solaris. Your mileage may vary. Good luck!
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- Larry Doolittle <LRDoolittle@lbl.gov> August 19, 1999
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