mirror of
https://github.com/steveicarus/iverilog.git
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158 lines
4.0 KiB
C++
158 lines
4.0 KiB
C++
/*
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* Copyright (c) 1998-2022 Stephen Williams ([email protected])
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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# include "config.h"
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# include "Module.h"
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# include "PGate.h"
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# include "PWire.h"
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# include "ivl_assert.h"
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using namespace std;
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list<Module::named_expr_t> Module::user_defparms;
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/* n is a permallocated string. */
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Module::Module(LexicalScope*parent, perm_string n)
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: PScopeExtra(n, parent)
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{
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library_flag = false;
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is_cell = false;
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is_interface = false;
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program_block = false;
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uc_drive = UCD_NONE;
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}
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Module::~Module()
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{
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}
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void Module::add_gate(PGate*gate)
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{
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gates_.push_back(gate);
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}
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unsigned Module::port_count() const
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{
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return ports.size();
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}
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/*
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* Return the array of PEIdent object that are at this port of the
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* module. If the port is internally unconnected, return an empty
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* array.
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*/
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const vector<PEIdent*>& Module::get_port(unsigned idx) const
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{
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ivl_assert(*this, idx < ports.size());
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static const vector<PEIdent*> zero;
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if (ports[idx])
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return ports[idx]->expr;
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else
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return zero;
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}
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unsigned Module::find_port(const char*name) const
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{
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ivl_assert(*this, name != 0);
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for (unsigned idx = 0 ; idx < ports.size() ; idx += 1) {
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if (ports[idx] == 0) {
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/* It is possible to have undeclared ports. These
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are ports that are skipped in the declaration,
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for example like so: module foo(x ,, y); The
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port between x and y is unnamed and thus
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inaccessible to binding by name. */
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continue;
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}
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ivl_assert(*this, ports[idx]);
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if (ports[idx]->name == name)
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return idx;
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}
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return ports.size();
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}
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perm_string Module::get_port_name(unsigned idx) const
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{
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ivl_assert(*this, idx < ports.size());
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if (ports[idx] == 0 || ports[idx]->name.str() == 0) {
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/* It is possible to have undeclared ports. These
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are ports that are skipped in the declaration,
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for example like so: module foo(x ,, y); The
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port between x and y is unnamed and thus
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inaccessible to binding by name. Port references
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that aren't simple or escaped identifiers are
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also inaccessible to binding by name. */
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return perm_string::literal("unnamed");
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}
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return ports[idx]->name;
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}
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PExpr* Module::get_port_default_value(unsigned idx) const
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{
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ivl_assert(*this, idx < ports.size());
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return ports[idx] ? ports[idx]->default_value : 0;
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}
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PGate* Module::get_gate(perm_string name)
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{
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for (list<PGate*>::iterator cur = gates_.begin()
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; cur != gates_.end() ; ++ cur ) {
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if ((*cur)->get_name() == name)
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return *cur;
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}
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return 0;
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}
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const list<PGate*>& Module::get_gates() const
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{
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return gates_;
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}
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PNamedItem::SymbolType Module::symbol_type() const
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{
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if (program_block)
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return PROGRAM;
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if (is_interface)
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return INTERFACE;
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return MODULE;
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}
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bool Module::can_be_toplevel() const
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{
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// Don't choose library modules.
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if (library_flag)
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return false;
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// Don't choose modules with parameters without default value
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for (std::map<perm_string,param_expr_t*>::const_iterator cur =
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parameters.begin(); cur != parameters.end(); ++cur) {
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if (cur->second->expr == 0)
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return false;
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}
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return true;
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}
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