51 lines
1.5 KiB
C++
51 lines
1.5 KiB
C++
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/*
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* VHDL code generator for Icarus Verilog.
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*
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* Copyright (C) 2008 Nick Gasson (nick@nickg.me.uk)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#include "vhdl_target.h"
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#include "vhdl_element.hh"
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#include <iostream>
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#include <fstream>
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extern "C" int target_design(ivl_design_t des)
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{
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ivl_scope_t *roots;
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unsigned int nroots;
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ivl_design_roots(des, &roots, &nroots);
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const char *ofname = ivl_design_flag(des, "-o");
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std::ofstream outfile(ofname);
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for (unsigned int i = 0; i < nroots; i++) {
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ivl_scope_t scope = roots[i];
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const char *scope_name = ivl_scope_basename(scope);
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// Dummy output to test regression script
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vhdl_entity test_ent(scope_name);
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vhdl_arch test_arch(scope_name);
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test_ent.emit(outfile);
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test_arch.emit(outfile);
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}
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outfile.close();
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return 0;
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}
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