42 lines
1.4 KiB
VHDL
42 lines
1.4 KiB
VHDL
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-- Copyright (c) 2015 CERN
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-- Maciej Suminski <maciej.suminski@cern.ch>
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--
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-- This source code is free software; you can redistribute it
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-- and/or modify it in source code form under the terms of the GNU
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-- General Public License as published by the Free Software
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-- Foundation; either version 2 of the License, or (at your option)
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-- any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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-- Test for concatenation of function call results.
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity concat_func is
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port(in_word : in std_logic_vector(7 downto 0);
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out_word : out std_logic_vector(7 downto 0));
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end entity concat_func;
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architecture test of concat_func is
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begin
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process(in_word)
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variable tmp : unsigned(7 downto 0);
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variable int : integer;
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begin
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tmp := unsigned(in_word);
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int := to_integer(tmp);
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out_word <= in_word(7 downto 6) & std_logic_vector(to_unsigned(int, 3)) & std_logic_vector(resize(tmp, 3));
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end process;
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end architecture test;
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