31 lines
480 B
Coq
31 lines
480 B
Coq
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// specify4.v
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module top;
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reg d, c;
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wire q;
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initial begin
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d = 0;
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c = 1;
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#10 $monitor($time,,"q=%b, d=%b, c=%b", q, d, c);
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#5 c = 0;
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#5 c = 1;
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#5 c = 0; d = 1;
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#5 c = 1;
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#5 c = 0; d = 0;
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#5 c = 1;
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#10 $finish(0);
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end
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mydff g1 (q, d, c);
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endmodule
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module mydff (output reg q, input d, input c);
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always @(posedge c) q <= d;
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specify
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(posedge c => (q +: d)) = (3, 2);
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endspecify
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endmodule
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