67 lines
1.5 KiB
Coq
67 lines
1.5 KiB
Coq
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// Copyright (c) 1999 Steven Wilson (stevew@home.com)
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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//
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// SDW - Identifies a scheduling bug. a1 should always follow a2, but it
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// seems IV has a race. d is set ONLY after a clock occurs, yet
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// a1 sets as if the clock hasn't occured??
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module test;
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parameter p_dly = 0;
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reg d,a1,a2,b2;
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reg err;
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reg clk;
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wire b1,c;
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always #5 clk = ~clk;
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assign #p_dly c = d;
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assign b1 = c;
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always @(c)
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b2 = c;
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always @(posedge clk)
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begin
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a1 <= b1;
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a2 <= b2;
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end
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always @(negedge clk)
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if(a1 != a2)
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err = 1;
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initial
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begin
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// $dumpfile("test.vcd");
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// $dumpvars(0,test);
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err = 0;
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clk = 0;
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d = 0;
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#20;
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@(posedge clk)
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d <= 1;
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#25;
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if(err == 1)
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$display("FAILED");
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else
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$display("PASSED");
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$finish;
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end
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endmodule
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