75 lines
2.1 KiB
Coq
75 lines
2.1 KiB
Coq
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/*
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* Copyright (c) 2003 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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/*
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* This sample demonstrates the post 20030904 Icarus Verilog feature
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* where combinational blocks with time-0 races against the rest of
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* the design can be resolved.
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*
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* The always @(foo) threads should be detected by the compiler as
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* combinational, and should be pushed to the front of the time-0
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* scheduling queue. This causes the threads to enter the wait early
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* so that it can detect the change from x to 1 for its value.
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*
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* The program HAS a time-0 race according to the IEEE1364 standard,
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* but Icarus Verilog as an extension resolves this race intentionally
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* as described.
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*/
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module main;
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reg foo, bar;
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reg foo_ok = 0, bar_ok = 0;
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initial foo = 1;
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always @(foo) begin
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if (foo !== 1'b1) begin
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$display("FAILED --(foo = %b)", foo);
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$finish;
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end
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foo_ok = 1;
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end
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always @(bar) begin
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if (bar !== 1'b1) begin
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$display("FAILED --(bar = %b)", bar);
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$finish;
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end
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bar_ok = 1;
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end
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initial bar = 1;
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initial begin
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#1 if (foo_ok !== 1) begin
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$display("FAILED -- foo lost the race");
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$finish;
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end
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if (bar_ok !== 1) begin
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$display("FAILED -- bar lost the race");
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$finish;
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end
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$display("PASSED");
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end // initial begin
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endmodule // main
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