32 lines
546 B
Coq
32 lines
546 B
Coq
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/*
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* Based on bug report PR#841
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*/
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module err ();
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reg clk;
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initial begin
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clk = 1'b1;
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#3 forever #10 clk=~clk;
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end
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always @(posedge clk) begin $display("PASSED"); $finish(0); end
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//wire kuku=clk;
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pll pll (clk);
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endmodule
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module pll (inclk0);
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input inclk0;
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tri0 inclk0;
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endmodule
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//this is example of running bug and not compilation bug.
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//if you will try to run it (a.out) after the compilation (iverilog try_err.v)
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//you will get an error ("./a.out:7: parse error")
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//from some unknown reason line 11 solve this problem.
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