68 lines
1.2 KiB
Coq
68 lines
1.2 KiB
Coq
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/* testcase */
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/**
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generate this input file:
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$ cat t.in
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1073741824
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2147483648
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4294967296
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$
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expected output in t.out:
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$ cat t.out
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# x = 1073741824
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# x = 2147483648
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# x = 4294967296
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0
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1073741824
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2147483648
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4294967296
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Icarus Verilog output in t.out:
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$ cat t.out
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# x = 1073741824
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# x = 2147483648
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# x = 4294967296
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0
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1073741824
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6442450944
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0
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*/
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module testbench;
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parameter WIDTH = 33;
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reg clk;
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reg [WIDTH-1:0] in;
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reg [WIDTH-1:0] test_val1;
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reg [WIDTH-1:0] test_val2;
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reg [WIDTH-1:0] test_val3;
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integer infile, outfile, count;
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initial begin
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clk = 0;
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in = 0;
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test_val1 = 1 << 30;
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test_val2 = 1 << 31;
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test_val3 = 1 << 32;
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infile = $fopen("ivltests/pr2029336.in", "r");
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outfile = $fopen("work/pr2029336.out", "w");
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$fwrite(outfile, "# x = %d\n", test_val1); // $fwrite() seems to be ok...
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$fwrite(outfile, "# x = %d\n", test_val2); // $fwrite() seems to be ok...
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$fwrite(outfile, "# x = %d\n", test_val3); // $fwrite() seems to be ok...
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end
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always @(negedge clk) begin
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$fwrite(outfile, "%d\n", in);
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count = $fscanf(infile, "%d\n", in); // $fscanf() seems buggy...
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if (count != 1) begin
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$fclose(infile);
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$fclose(outfile);
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$finish;
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end
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end
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always #1
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clk = ~clk;
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endmodule
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