60 lines
1.4 KiB
Coq
60 lines
1.4 KiB
Coq
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module test;
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initial begin: A
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reg [4:0] a;
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reg [31:0] b, c, d;
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a = 5'h14;
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b = $signed(a);
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c = {_$Finv5(_$Fsub8(_$Fadd8((32'haa ^ (32'hcc & _$Fsll32(_$Fsrl32(_$Fsll32(32'h78, 32'h2), 32'h3), 32'h1))), 32'h69), (32'h50 * 32'h2)))};
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d = $signed(_$Finv5(_$Fsub8(_$Fadd8((32'haa ^ (32'hcc & _$Fsll32(_$Fsrl32(_$Fsll32(32'h78, 32'h2), 32'h3), 32'h1))), 32'h69), (32'h50 * 32'h2))));
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$write("a is %0h; b is %0h; c is %0h; d is %0h\n", a, b, c, d);
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end
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function [4:0] _$Finv5;
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input l;
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reg [4:0] l;
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_$Finv5 = ~l;
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endfunction
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function [7:0] _$Fsub8;
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input l,r;
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reg [7:0] l,r;
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_$Fsub8 = l-r;
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endfunction
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function [7:0] _$Fadd8;
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input l,r;
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reg [7:0] l,r;
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_$Fadd8 = l+r;
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endfunction
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function [31:0] _$Fsll32;
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input l,r;
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reg [31:0] l;
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integer r;
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begin
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if(r < 0) begin
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if(r + 32 <= 0) _$Fsll32 = 32'b0;
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else _$Fsll32 = l >> -r;
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end else if(r > 0) begin
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if(r >= 32) _$Fsll32 = 32'b0;
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else _$Fsll32 = l << r;
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end else _$Fsll32 = l;
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end
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endfunction
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function [31:0] _$Fsrl32;
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input l,r;
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reg [31:0] l;
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integer r;
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begin
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if(r < 0) begin
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if(r + 32 <= 0) _$Fsrl32 = 32'b0;
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else _$Fsrl32 = l << -r;
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end else if(r > 0) begin
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if(r >= 32) _$Fsrl32 = 32'b0;
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else _$Fsrl32 = l >> r;
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end else _$Fsrl32 = l;
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end
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endfunction
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endmodule
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