20 lines
291 B
Coq
20 lines
291 B
Coq
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module test(CL, Q_data, D);
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parameter
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Bits = 84;
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input CL;
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output [Bits-1 : 0] Q_data;
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input [Bits-1 : 0] D;
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reg WENreg;
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reg ICGFlag;
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specify
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specparam
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taa = 1.0;
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if (WENreg && !ICGFlag) (CL *> (Q_data[0] : D[0])) = (taa, taa);
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endspecify
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endmodule
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