26 lines
547 B
Coq
26 lines
547 B
Coq
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module test;
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// This example was adapted from:
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// DRAFT STANDARD VERILOG HARDWARE DESCRIPTION LANGUAGE
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// IEEE P1364-2005/D3, 1/7/04
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// Section 4.4.2 "An example of an expression bit-length problem"
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// pg. 59
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reg [15:0] a, b, answer; // 16-bit regs
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initial
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begin
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a = 16'h8000;
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b = 16'h8000;
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answer = (a + b + 0) >> 1; //will work correctly
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if ( answer != 16'h8000 )
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begin
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$display("FAILED -- expected 16'h8000 received 16'h%h", answer);
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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